Intel 8XC196NP, 80C196NU, Microcontroller manual ← Dest MOD SRC, Djnz Decrement and Jump if not Zero

8XC196NP, 80C196NU USER’S MANUAL

Table A-6. Instruction Set (Continued)

Mnemonic

Operation

Instruction Format

DIVU

DIVIDE WORDS, UNSIGNED. Divides the

DEST, SRC

contents of the destination double-word

DIVU

lreg, waop

operand by the contents of the source word

(100011aa) (waop) (lreg)

operand, using unsigned arithmetic. It stores

the quotient into the low-order word (i.e., the

word with the lower address) of the

destination operand and the remainder into

the high-order word. The following two

statements are performed concurrently.

(low word DEST) ← (DEST) / (SRC)

(high word DEST)

← (DEST) MOD (SRC)

PSW Flag Settings

Z

N

C

V

VT

ST

—

—

—

✓

−

—

DIVUB

DIVIDE BYTES, UNSIGNED. This instruction

DEST, SRC

divides the contents of the destination word

DIVUB

wreg, baop

operand by the contents of the source byte

(100111aa) (baop) (wreg)

operand, using unsigned arithmetic. It stores

the quotient into the low-order byte (i.e., the

byte with the lower address) of the

destination operand and the remainder into

the high-order byte. The following two

statements are performed concurrently.

(low byte DEST) ← (DEST) / (SRC)

(high byte DEST) ←

(DEST) MOD (SRC)

PSW Flag Settings

Z

N

C

V

VT

ST

—

—

—

✓

−

—

DJNZ

DECREMENT AND JUMP IF NOT ZERO.

Decrements the value of the byte operand by

DJNZ

breg,cadd

1. If the result is 0, control passes to the next

(11100000) (breg) (disp)

sequential instruction. If the result is not 0,

the instruction adds to the program counter

the offset between the end of this instruction

NOTE: The displacement (disp) is sign-

and the target label, effecting the jump. The

extended to 24 bits.

offset must be in the range of –128 to +127.

(COUNT) ← (COUNT) –1

if (COUNT) ≠

0 then

PC ← PC + 8-bit disp

end_if

PSW Flag Settings

Z

N

C

V

VT

ST

—

—

—

—

—

—

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