Intel Microcontroller, 80C196NU, 8XC196NP manual Range of 0 to 31 1FH, inclusive. If

INSTRUCTION SET REFERENCE

Table A-6. Instruction Set (Continued)

Mnemonic			Operation						Instruction Format
SHRA	ARITHMETIC RIGHT SHIFT WORD. Shifts
	the destination word operand to the right as							SHRA	wreg,#count
	many times as specified by the count
								(00001010) (count) (wreg)
	operand. The count may be specified either
	as an immediate value in the range of 0 to 15							or
	(0FH), inclusive, or as the content of any							SHRA	wreg,breg
	register (10H – 0FFH) with a value in the
								(00001010) (breg) (wreg)
	range of 0 to 31 (1FH), inclusive. If the
	original high order bit value was “0,” zeros are
	shifted in. If the value was “1,” ones are							NOTES:	This instruction clears the
	shifted in. The last bit shifted out is saved in
									sticky bit flag at the beginning
	the carry flag.
									of the instruction. If at any time
	Temp ← (COUNT)
									during the shift a “1” is shifted
	do while Temp ≠ 0								into the carry flag and another
	C ← Low order bit of (DEST)								shift cycle occurs, the instruc-
	(DEST) ← (DEST)/2								tion sets the sticky bit flag.
	Temp ← Temp – 1
	end_while								In this operation, DEST/2 rep-
									resents signed division.
			PSW Flag Settings
		Z	N	C	V	VT	ST
		✓	✓	✓	0	—	✓
SHRAB	ARITHMETIC RIGHT SHIFT BYTE. Shifts the
	destination byte operand to the right as many							SHRAB	breg,#count
	times as specified by the count operand. The
								(00011010) (count) (breg)
	count may be specified either as an
								or
	immediate value in the range of 0 to 15
	(0FH), inclusive, or as the content of any							SHRAB	breg,breg
	register (10H – 0FFH) with a value in the
								(00011010) (breg) (breg)
	range of 0 to 31 (1FH), inclusive. If the
	original high order bit value was “0,” zeros are
	shifted in. If the value was “1,” ones are							NOTES:	This instruction clears the
	shifted in. The last bit shifted out is saved in
									sticky bit flag at the beginning
	the carry flag.
									of the instruction. If at any time
	Temp ← (COUNT)
									during the shift a “1” is shifted
	do while Temp ≠ 0								into the carry flag and another
	C = Low order bit of (DEST)								shift cycle occurs, the instruc-
	(DEST) ← (DEST)/2								tion sets the sticky bit flag.
	Temp ← Temp – 1								In this operation, DEST/2 rep-
	end_while
									resents signed division.
			PSW Flag Settings
		Z	N	C	V	VT	ST
		✓	✓	✓	0	—	✓

A-39