Interrupt Sources, Vectors, and Priorities | Intel 8XC196NP specification

STANDARD AND PTS INTERRUPTS

Table 6-3. Interrupt Sources, Vectors, and Priorities

		Interrupt Controller			PTS Service
			Service		PTS Service
			Service
Interrupt Source	Mnemonic
Interrupt Source	Mnemonic	Name	Vector	Priority	Name		Vector	Priority
		Name	Vector	Priority	Name		Vector	Priority

Nonmaskable Interrupt	NMI	INT15	FF203EH	30	—		—	—
EXTINT3 Pin	EXTINT3	INT14	FF203CH	14	PTS14	FF205CH		29
EXTINT2 Pin	EXTINT2	INT13	FF203AH	13	PTS13	FF205AH		28
EPA capture overrun in	OVR2_3 †	INT12	FF2038H	12	PTS12	FF2058H		27
channel 2 or 3	OVR2_3 †	INT12	FF2038H	12	PTS12	FF2058H		27
channel 2 or 3
EPA capture overrun in	OVR0_1 †	INT11	FF2036H	11	PTS11	FF2056H		26
channel 0 or 1	OVR0_1 †	INT11	FF2036H	11	PTS11	FF2056H		26
channel 0 or 1
EPA Capture/Compare 3	EPA3	INT10	FF2034H	10	PTS10	FF2054H		25
EPA Capture/Compare 2	EPA2	INT09	FF2032H	09	PTS09	FF2052H		24
EPA Capture/Compare 1	EPA1	INT08	FF2030H	08	PTS08	FF2050H		23
Unimplemented Opcode	—	—	FF2012H	—	—	—	—
Software TRAP Instruction	—	—	0FF2010H	—	—	—	—
EPA Capture/Compare 0	EPA0	INT07	FF200EH	07	PTS07	FF204EH		22
SIO Receive	RI	INT06	FF200CH	06	PTS06	FF204CH		21
SIO Transmit	TI	INT05	FF200AH	05	PTS05	FF204AH		20
EXTINT1 Pin	EXTINT1	INT04	FF2008H	04	PTS04	FF2048H		19
EXTINT0 Pin	EXTINT0	INT03	FF2006H	03	PTS03	FF2046H		18
Reserved	Reserved	INT02	FF2004H	02	PTS02	FF2044H		17
Timer 2 Overflow	OVRTM2	INT01	FF2002H	01	PTS01	FF2042H		16
Timer 1 Overflow	OVRTM1	INT00	FF2000H	00	PTS00	FF2040H		15

†PTS service is not recommended because the PTS cannot determine the source of shared interrupts.

6.3.1.1Unimplemented Opcode

If the CPU attempts to execute an unimplemented opcode, an indirect vector through location FF2012H occurs. This prevents random software execution during hardware and software fail- ures. The interrupt vector should contain the starting address of an error routine that will not fur- ther corrupt an already erroneous situation. The unimplemented opcode interrupt prevents other interrupt requests from being acknowledged until after the next instruction is executed.

6.3.1.2Software Trap

The TRAP instruction (opcode F7H) causes an interrupt call that is vectored through location FF2010H. The TRAP instruction provides a single-instruction interrupt that is useful when de- bugging software or generating software interrupts. The TRAP instruction prevents other inter- rupt requests from being acknowledged until after the next instruction is executed.

6-5

Microcontroller, 80C196NU, 8XC196NP specifications

The Intel 8XC196NP and 80C196NU microcontrollers are part of Intel's renowned 16-bit microcontroller series that gained popularity in the 1980s and 1990s for embedded systems applications. Designed for a variety of applications, these microcontrollers are characterized by their robust performance, versatility, and industry-standard architecture.

The 8XC196NP features an enhanced instruction set with over 100 instructions, allowing for efficient code execution. It operates at clock speeds up to 16 MHz, which contributes to improved performance in time-sensitive applications. The microcontroller is equipped with a 16-bit data bus, enabling more efficient data handling compared to its 8-bit predecessors, thus accommodating complex algorithms and large data sets.

In terms of memory architecture, the 8XC196NP supports an addressable memory space of up to 64 KB of program memory and 64 KB of data memory. This configuration provides sufficient space for large applications while ensuring fast data access. The microcontroller includes integrated features such as timers, serial I/O capabilities, and interrupt processing, which enhance its functionality for real-time applications and control mechanisms.

The 80C196NU, on the other hand, is designed for lower power operation, making it suitable for battery-powered devices. This microcontroller maintains similar features to the 8XC196NP while offering advancements that support low-power consumption. The 80C196NU can also function in a range of temperature environments, making it adaptable for industrial applications.

Both the 8XC196NP and 80C196NU support external memory interfacing, allowing designers to expand the system's capability by connecting additional ROM and RAM. This flexibility makes them appealing for developing complex systems, such as motor controls, industrial automation, and consumer electronics.

Another standout feature of these microcontrollers is their built-in debugging capabilities. Intel provided hardware and software tools that enabled developers to test and troubleshoot their applications effectively, reducing the development time and increasing reliability.

Overall, the Intel 8XC196NP and 80C196NU microcontrollers stand out for their dependability, versatility, and performance, contributing significantly to the evolution of embedded system design. Their legacy continues to influence modern microcontroller technology, ensuring their relevance in a wide array of applications today.

Intel 8XC196NP Interrupt Sources, Vectors, and Priorities, Unimplemented Opcode, Software Trap

Models: Microcontroller 80C196NU 8XC196NP

Table 6-3. Interrupt Sources, Vectors, and Priorities

Interrupt Controller

PTS Service