Intel 8XC196NP, 80C196NU, Microcontroller manual RET Cseg AT 0FF200CH

8XC196NP, 80C196NU USER’S MANUAL

SERIAL_RI_ISR:
PUSHA	; Save PSW, INT_MASK, INT_MASK1, & WSR
	; (this disables all interrupts)
LDB INT_MASK1, #01000000B	; Enable EXTINT3 only
EI	; Enable interrupt servicing
	; Service the RI interrupt
POPA	; Restore PSW, INT_MASK, INT_MASK1, &
	; WSR registers
RET
CSEG AT 0FF200CH	; fill in interrupt table
DCW LSW SERIAL_RI_ISR	; LSW is a compiler directive that means
	; least-significant word of vector address
END

Note that location FF200CH in the interrupt vector table must be loaded with the value of the la- bel SERIAL_RI_ISR before the interrupt request occurs and that the receive interrupt must be enabled for this routine to execute.

This routine, like all interrupt service routines, is handled in the following manner:

1.After the hardware detects and prioritizes an interrupt request, it generates and executes an interrupt call. This pushes the program counter onto the stack and then loads it with the contents of the vector corresponding to the highest priority, pending, unmasked interrupt. The hardware will not allow another interrupt call until after the first instruction of the interrupt service routine is executed.

2.The PUSHA instruction saves the contents of the PSW, INT_MASK, INT_MASK1, and window selection register (WSR) onto the stack and then clears the PSW, INT_MASK, and INT_MASK1 registers. In addition to the arithmetic flags, the PSW contains the global interrupt enable bit (I) and the PTS enable bit (PSE). By clearing the PSW and the interrupt mask registers, PUSHA effectively masks all maskable interrupts, disables standard interrupt servicing, and disables the PTS. Because PUSHA is a protected instruction, it also inhibits interrupt calls until after the next instruction executes.

3.The LDB INT_MASK1 instruction enables those interrupts that you choose to allow to interrupt the service routine. In this example, only EXTINT3 can interrupt the receive interrupt service routine. By enabling or disabling interrupts, the software establishes its own interrupt servicing priorities.

4.The EI instruction re-enables interrupt processing and inhibits interrupt calls until after the next instruction executes.

5.The actual interrupt service routine executes within the priority structure established by the software.

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