Intel Microcontroller, 80C196NU, 8XC196NP manual Memory Controller, Instruction Format

ARCHITECTURAL OVERVIEW

2.3.3.2Instruction Format

MCS 96 microcontrollers combine a large set of general-purpose registers with a three-operand instruction format. This format allows a single instruction to specify two source registers and a separate destination register. For example, the following instruction multiplies two 16-bit vari- ables and stores the 32-bit result in a third variable.

MUL RESULT, FACTOR_1, FACTOR_2	;multiply FACTOR_1 and FACTOR_2
	;and store answer in RESULT
	;(RESULT)←(FACTOR_1 × FACTOR_2)

An 80C186 device requires four instructions to accomplish the same operation. The following ex- ample shows the equivalent code for an 80C186 device.

MOV	AX, FACTOR_1	;move FACTOR_1 into accumulator (AX)
		;(AX)←FACTOR1
MUL	FACTOR_2	;multiply FACTOR_2 and AX
		;(DX:AX)←(AX)×(FACTOR_2)
MOV	RESULT, AX	;move lower byte into RESULT
		;(RESULT)←(AX)
MOV	RESULT+2, DX	;move upper byte into RESULT+2
		;(RESULT+2)←(DX)

2.3.4Memory Controller

The RALU communicates with all memory, except the register file and peripheral SFRs, through the memory controller. (It communicates with the upper register file through the memory control- ler except when windowing is used; see Chapter 5, “Memory Partitions,”) The memory controller contains the prefetch queue, the slave program counter (slave PC), address and data registers, and the bus controller.

The bus controller drives the memory bus, which consists of an internal memory bus and the ex- ternal address/data bus. The bus controller receives memory-access requests from either the RALU or the prefetch queue; queue requests always have priority. This queue is transparent to the RALU and your software.

NOTE

When using a logic analyzer to debug code, remember that instructions are preloaded into the prefetch queue and are not necessarily executed immediately after they are fetched.

When the bus controller receives a request from the queue, it fetches the code from the address contained in the slave PC. The slave PC increases execution speed because the next instruction byte is available immediately and the processor need not wait for the master PC to send the ad- dress to the memory controller. If a jump, interrupt, call, or return changes the address sequence, the master PC loads the new address into the slave PC, then the CPU flushes the queue and con- tinues processing.

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