Intel 80C196NU, 8XC196NP manual Mnemonic Operation Instruction Format, Count ← Count, PC ← Dest

Models: Microcontroller 80C196NU 8XC196NP

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8XC196NP, 80C196NU USER’S MANUAL

Table A-6. Instruction Set (Continued)

Mnemonic

 

 

 

Operation

 

 

 

 

 

Instruction Format

 

 

 

 

 

BMOVI

INTERRUPTIBLE BLOCK MOVE. Moves a

 

PTRS, CNTREG

 

block of word data from one location in

BMOVI

lreg, wreg

 

memory to another. The instruction is

 

(11001101) (wreg) (lreg)

 

identical to BMOV, except that BMOVI is

 

 

 

 

interruptible. The source and destination

 

 

 

addresses are calculated using the indirect

NOTE: The pointers are autoincre-

 

with autoincrement addressing mode. A long

 

 

mented during this instruction.

 

register (PTRS) addresses the source and

 

 

 

However, CNTREG is decre-

 

destination pointers, which are stored in

 

 

 

mented only when the instruction

 

adjacent word registers. The source pointer

 

 

 

is interrupted. When BMOVI is

 

(SRCPTR) is the low word and the

 

 

 

 

 

 

 

interrupted, CNTREG is updated

 

destination pointer (DSTPTR) is the high

 

 

 

to store the interim word count at

 

word of PTRS. A word register (CNTREG)

 

 

 

the time of the interrupt. For this

 

specifies the number of transfers. The blocks

 

 

 

reason, you should always reload

 

of data can be located anywhere in page 00H

 

 

 

CNTREG before starting a

 

of register RAM, but should not overlap.

 

 

 

BMOVI.

 

Because the source (SRCPTR) and

 

 

 

 

 

destination (DSTPTR) pointers are 16 bits

 

 

 

wide, this instruction uses nonexteneded

 

 

 

data moves. It cannot operate across page

 

 

 

boundaries. (If you need to cross page

 

 

 

boundaries, use the EBMOVI instruction.)

 

 

 

PTSSRC and PTSDST will operate from the

 

 

 

page defined by EP_REG. EP_REG should

 

 

 

be set to 00H to select page 00H (see

 

 

 

“Accessing Data” on page 5-23). (The

 

 

 

80C196NU forces EP_REG to 00H.)

 

 

 

COUNT (CNTREG)

 

 

 

 

 

 

 

 

LOOP: SRCPTR (PTRS)

 

 

 

 

 

 

 

DSTPTR (PTRS + 2)

 

 

 

 

 

 

 

 

(DSTPTR) (SRCPTR)

 

 

 

 

 

 

 

(PTRS) SRCPTR + 2

 

 

 

 

 

 

 

 

(PTRS + 2)

DSTPTR + 2

 

 

 

 

 

 

 

COUNT COUNT – 1

 

 

 

 

 

 

 

 

if COUNT 0 then

 

 

 

 

 

 

 

 

go to LOOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSW Flag Settings

 

 

 

 

 

 

Z

N

 

C

V

VT

ST

 

 

 

 

 

— — — — — —

 

 

 

 

 

 

 

 

BR

BRANCH INDIRECT. Continues execution at

 

DEST

 

the address specified in the operand word

BR

[wreg]

 

register.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(11100011) (wreg)

 

PC (DEST)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE:

In 1-Mbyte mode, the BR instruc-

 

 

 

PSW Flag Settings

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tion always branches to page

 

 

Z

N

 

C

 

V

VT

 

ST

 

 

 

 

 

 

 

 

 

FFH. Use the EBR instruction to

 

 

— —

 

 

 

 

 

 

 

 

 

 

 

 

branch to an address on any other

 

 

 

 

 

 

 

 

 

 

 

 

 

page.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A-10

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Intel 80C196NU, 8XC196NP, Microcontroller manual Mnemonic Operation Instruction Format, Count ← Count, PC ← Dest

Microcontroller, 80C196NU, 8XC196NP specifications

The Intel 8XC196NP and 80C196NU microcontrollers are part of Intel's renowned 16-bit microcontroller series that gained popularity in the 1980s and 1990s for embedded systems applications. Designed for a variety of applications, these microcontrollers are characterized by their robust performance, versatility, and industry-standard architecture.

The 8XC196NP features an enhanced instruction set with over 100 instructions, allowing for efficient code execution. It operates at clock speeds up to 16 MHz, which contributes to improved performance in time-sensitive applications. The microcontroller is equipped with a 16-bit data bus, enabling more efficient data handling compared to its 8-bit predecessors, thus accommodating complex algorithms and large data sets.

In terms of memory architecture, the 8XC196NP supports an addressable memory space of up to 64 KB of program memory and 64 KB of data memory. This configuration provides sufficient space for large applications while ensuring fast data access. The microcontroller includes integrated features such as timers, serial I/O capabilities, and interrupt processing, which enhance its functionality for real-time applications and control mechanisms.

The 80C196NU, on the other hand, is designed for lower power operation, making it suitable for battery-powered devices. This microcontroller maintains similar features to the 8XC196NP while offering advancements that support low-power consumption. The 80C196NU can also function in a range of temperature environments, making it adaptable for industrial applications.

Both the 8XC196NP and 80C196NU support external memory interfacing, allowing designers to expand the system's capability by connecting additional ROM and RAM. This flexibility makes them appealing for developing complex systems, such as motor controls, industrial automation, and consumer electronics.

Another standout feature of these microcontrollers is their built-in debugging capabilities. Intel provided hardware and software tools that enabled developers to test and troubleshoot their applications effectively, reducing the development time and increasing reliability.

Overall, the Intel 8XC196NP and 80C196NU microcontrollers stand out for their dependability, versatility, and performance, contributing significantly to the evolution of embedded system design. Their legacy continues to influence modern microcontroller technology, ensuring their relevance in a wide array of applications today.