Intel Microcontroller, 80C196NU, 8XC196NP manual Design Considerations

I/O PORTS

3.Any nonextended or direct instruction that accesses the register file or the windowable SFRs is always directed internally to these areas, regardless of the page from which code is executing. This effectively maps the register file and windowable SFRs into every page. Extended instructions can access the “mapped over” areas of each page, as shown in the following code example.

EST 1CH, 01001CH[0] ;reg 1CH stored at memory location 01001CH

7.3.3.4Design Considerations

At the end of EPORT bus activity and during periods of internal bus activity, EPORT pins con- tinue to drive the last data address that was output. If these lines are being used to enable external memory, that memory will remain enabled until a different page is accessed.

During the CCB fetch, all EPORT lines are strongly driven high. Designers should ensure that this does not conflict with external systems that are outputting signals to the EPORT.

When EPORT pins are floated during idle, powerdown, or hold, the external system must provide circuitry to prevent CMOS inputs on external devices from floating. During powerdown, the EPORT input buffers on pins configured for their extended-address function are disconnected from the pins, so a floating pin will not cause increased power consumption.

Open-drain outputs require an external pull-up resistor. Inputs must be driven or pulled high or low; they must not be allowed to float.

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