Package Diagrams | Cypress CY7C1382F, CY7C1380F, CY7C1380D, CY7C1382D

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Package Diagrams

Figure 14. 100-Pin Thin Plastic Quad Flat Pack (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

14.00±0.10

100

81

1

22.00±0.20

20.00±0.10

30

31

50

80

0.30±0.08

0.65

TYP.

51

12° ±1° (8X)

1.40±0.05

SEE DETAIL

A

0.20 MAX.

1.60 MAX.

R 0.08 MIN. 0.20 MAX.

0.25

0° MIN.

STAND-OFF 0.05 MIN. 0.15 MAX.

SEATING PLANE

NOTE:

0.10

GAUGE PLANE

0° -7°

0.60±0.15

1.00 REF.

R 0.08 MIN. 0.20 MAX.

0.20 MIN.

DETAIL A

1.JEDEC STD REF MS-026

2.BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3.DIMENSIONS IN MILLIMETERS

51-85050-*B

Document #: 38-05543 Rev. *F

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Cypress CY7C1382F, CY7C1380F, CY7C1380D, CY7C1382D manual Package Diagrams, Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm

Contents

Selection Guide FeaturesFunctional Description Description 250 MHz 200 MHz 167 MHz Unit Logic Block Diagram CY7C1380D/CY7C1380F 3 512K x Logic Block Diagram CY7C1382D/CY7C1382F 3 1M x Pin Configurations Pin Tqfp Pinout 3-Chip Enable Ball BGA Pinout Ball Fbga Pinout 3-Chip Enable Pin Definitions Name Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the core of the device Pin Definitions TMSTCK Jtag Single Write Accesses Initiated by Adsc Single Write Accesses Initiated by AdspSingle Read Accesses Functional Overview Address Sleep ModeBurst Sequences A1 A0 Parameter Description Test Conditions Min Truth Table Operation Add. Used Truth Table for Read/Write 4 Function CY7C1380D/CY7C1380FFunction CY7C1382D/CY7C1382F TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass Register Parameter Description Min TAP TimingReserved Clock 5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Parameter Description Test Conditions Min Identification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit Size Ball BGA Boundary Scan Order 14 Bit # Ball ID A10 B10 P10 Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Range Ambient Package CapacitanceThermal Resistance EIA/JESD51 AC Test Loads and Waveforms 3V I/O Test Load 5V I/O Test Load Switching Characteristics Over the Operating Range 20 Setup TimesOutput Times Switching Waveforms Read Cycle Timing Write Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Package Diagrams Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Submission Orig. Description of Change Date Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB