Contents
Main
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Features
Functional Description
Selection Guide
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F
Logic Block Diagram CY7C1380D/CY7C1380F [3] (512K x 36)
WRITE DRIVER
GW
CE
Page
119-Ball BGA Pinout
165-Ball FBGA Pinout (3-Chip Enable)
2345671 A B C D E F G H J K L M N P R
891011
2345671 A B C D E F G H J K L M N P R
891011
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F
Functional Overview
Single Read Accesses
Single Write Accesses Initiated by ADSP
Single Write Accesses Initiated by ADSC
Burst Sequences
Sleep Mode
Truth Table
Truth Table for Read/Write
IEEE 1149.1 Serial Boundary Scan (JTAG)
Disabling the JTAG Feature
TAP Controller State Diagram
Test Access Port (TAP)
TAP Controller Block Diagram
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F
TAP Instruction Set
Reserved
TAP Ti min g
TAP AC Switching Characteristics Over the Operating Range [10, 11]
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
TAP DC Electrical Characteristics And Operating Conditions
Identification Register Definitions
Scan Register Sizes
Identification Codes
119-Ball BGA Boundary Scan Order[14, 15]
165-Ball BGA Boundary Scan Order [14, 16]
Maximum Ratings
Operating Range
Electrical Characteristics
Capacitance
Thermal Resistance
Figure 9. AC Test Loads and Waveforms
= 1.5V
(c)
(a) (b)
V
Switching Characteristics
Switching Waveforms
Figure 10. Read Cycle Timing
Figure 11. Write Cycle Timing
27.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Figure 12. Read/Write Cycle Timing
Figure 13. ZZ Mode Timing
Ordering Information
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Package Diagrams
Figure 14. 100-Pin Thin Plastic Quad Flat Pack (14 x 20 x 1.4 mm) (51-85050)
A
Page
Figure 16. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
Package Diagrams
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
1.40 MAX.
51-85180-*A
SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
Document History Page
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