ZZ Mode Timing 30 | Cypress CY7C1382F, CY7C1380F, CY7C1380D instruction

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F

Switching Waveforms

CLK

I SUPPLY

ALL INPUTS (except ZZ)

Outputs (Q)

(continued)

Figure 13. ZZ Mode Timing [30, 31]

tZZ

t ZZI

I DDZZ

High-Z

DON’T CARE

t ZZREC

t RZZI

DESELECT or READ Only

Notes

30.Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.

31.DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05543 Rev. *F

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Cypress CY7C1382F, CY7C1380F, CY7C1380D, CY7C1382D manual ZZ Mode Timing 30

Contents

Selection Guide FeaturesFunctional Description Description 250 MHz 200 MHz 167 MHz Unit Logic Block Diagram CY7C1380D/CY7C1380F 3 512K x Logic Block Diagram CY7C1382D/CY7C1382F 3 1M x Pin Configurations Pin Tqfp Pinout 3-Chip Enable Ball BGA Pinout Ball Fbga Pinout 3-Chip Enable Pin Definitions Name Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the core of the device TCK Jtag Pin DefinitionsTMS Single Write Accesses Initiated by Adsc Single Write Accesses Initiated by AdspSingle Read Accesses Functional Overview Address Sleep ModeBurst Sequences A1 A0 Parameter Description Test Conditions Min Truth Table Operation Add. Used Function CY7C1382D/CY7C1382F Truth Table for Read/Write 4Function CY7C1380D/CY7C1380F Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Bypass Register Parameter Description Min TAP TimingReserved Clock 5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Parameter Description Test Conditions Min Identification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit Size Ball BGA Boundary Scan Order 14 Bit # Ball ID A10 B10 P10 Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Range Ambient Package CapacitanceThermal Resistance EIA/JESD51 AC Test Loads and Waveforms 3V I/O Test Load 5V I/O Test Load Output Times Switching Characteristics Over the Operating Range 20Setup Times Switching Waveforms Read Cycle Timing Write Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Package Diagrams Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Submission Orig. Description of Change Date USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions