Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress CY7C1382D, CY7C1380F, CY7C1380D manual Pin Configurations, Pin Tqfp Pinout 3-Chip Enable

Models: CY7C1380D CY7C1380F CY7C1382D CY7C1382F

1 34

Download 34 pages 5.5 Kb

Page 3

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Pin Configurations

100-Pin TQFP Pinout (3-Chip Enable)

Figure 1. CY7C1380D, CY7C1380F(512K X 36)

Figure 2. CY7C1382D, CY7C1382F (1M X 18)

Document #: 38-05543 Rev. *F

Page 3 of 34

[+] Feedback

Image 3

Cypress CY7C1382D, CY7C1380F, CY7C1380D, CY7C1382F manual Pin Configurations, Pin Tqfp Pinout 3-Chip Enable

Contents

Description 250 MHz 200 MHz 167 MHz Unit FeaturesFunctional Description Selection Guide Logic Block Diagram CY7C1382D/CY7C1382F 3 1M x Logic Block Diagram CY7C1380D/CY7C1380F 3 512K x Pin Tqfp Pinout 3-Chip Enable Pin Configurations Ball BGA Pinout Ball Fbga Pinout 3-Chip Enable Ground for the core of the device Power supply inputs to the core of the devicePower supply for the I/O circuitry Pin Definitions Name Description Pin Definitions TMSTCK Jtag Functional Overview Single Write Accesses Initiated by AdspSingle Read Accesses Single Write Accesses Initiated by Adsc A1 A0 Parameter Description Test Conditions Min Sleep ModeBurst Sequences Address Operation Add. Used Truth Table Truth Table for Read/Write 4 Function CY7C1380D/CY7C1380FFunction CY7C1382D/CY7C1382F TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction Set Clock TAP TimingReserved Parameter Description Min Parameter Description Test Conditions Min TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test Conditions Register Name Bit Size Identification Register DefinitionsScan Register Sizes Identification Codes Bit # Ball ID Ball BGA Boundary Scan Order 14 A10 B10 P10 Range Ambient Electrical Characteristics Over the Operating RangeMaximum Ratings Operating Range EIA/JESD51 CapacitanceThermal Resistance Package 5V I/O Test Load AC Test Loads and Waveforms 3V I/O Test Load Switching Characteristics Over the Operating Range 20 Setup TimesOutput Times Read Cycle Timing Switching Waveforms Write Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Package Diagrams Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Submission Orig. Description of Change Date Document History Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB