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Cypress CY7C1380F, CY7C1380D, CY7C1382F, CY7C1382D manual 200

Models: CY7C1380D CY7C1380F CY7C1382D CY7C1382F

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

	Speed		Package	Part and Package Type	Operating
	(MHz)	Ordering Code	Diagram	Part and Package Type	Range
	(MHz)	Ordering Code	Diagram		Range
	200	CY7C1380D-200AXC	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free	Commercial

		CY7C1382D-200AXC

		CY7C1380F-200AXC

		CY7C1382F-200AXC

		CY7C1380F-200BGC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

		CY7C1382F-200BGC

		CY7C1380F-200BGXC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

		CY7C1382F-200BGXC

		CY7C1380D-200BZC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

		CY7C1382D-200BZC

		CY7C1380F-200BZC

		CY7C1382F-200BZC

		CY7C1380D-200BZXC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

		CY7C1382D-200BZXC

		CY7C1380F-200BZXC

		CY7C1382F-200BZXC

		CY7C1380D-200AXI	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free	Industrial

		CY7C1382D-200AXI

		CY7C1380F-200AXI

		CY7C1382F-200AXI

		CY7C1380F-200BGI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

		CY7C1382F-200BGI

		CY7C1380F-200BGXI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

		CY7C1382F-200BGXI

		CY7C1380D-200BZI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

		CY7C1382D-200BZI

		CY7C1380F-200BZI

		CY7C1382F-200BZI

		CY7C1380D-200BZXI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

		CY7C1382D-200BZXI

		CY7C1380F-200BZXI

		CY7C1382F-200BZXI

Document #: 38-05543 Rev. *F

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Cypress CY7C1380F, CY7C1380D, CY7C1382F, CY7C1382D manual 200

Contents

Features Functional DescriptionSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1380D/CY7C1380F 3 512K x Logic Block Diagram CY7C1382D/CY7C1382F 3 1M xPin Configurations Pin Tqfp Pinout 3-Chip EnableBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Power supply inputs to the core of the device Power supply for the I/O circuitryPin Definitions Name Description Ground for the core of the deviceTMS Pin DefinitionsTCK Jtag Single Write Accesses Initiated by Adsp Single Read AccessesSingle Write Accesses Initiated by Adsc Functional OverviewSleep Mode Burst SequencesAddress A1 A0 Parameter Description Test Conditions MinTruth Table Operation Add. UsedFunction CY7C1380D/CY7C1380F Truth Table for Read/Write 4Function CY7C1382D/CY7C1382F TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterTAP Timing ReservedParameter Description Min ClockTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA10 B10 P10 Electrical Characteristics Over the Operating Range Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistancePackage EIA/JESD51AC Test Loads and Waveforms 3V I/O Test Load 5V I/O Test LoadSetup Times Switching Characteristics Over the Operating Range 20Output Times Switching Waveforms Read Cycle TimingWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Package Diagrams Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Submission Orig. Description of Change DateWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB