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Cypress CY7C1380F, CY7C1380D, CY7C1382F manual Capacitance, Thermal Resistance, Package, EIA/JESD51

Models: CY7C1380D CY7C1380F CY7C1382D CY7C1382F

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Capacitance [19]

	Parameter	Description	Test Conditions	100 TQFP	119 BGA	165 FBGA	Unit
	Parameter	Description	Test Conditions	Package	Package	Package	Unit
				Package	Package	Package
	CIN	Input Capacitance	TA = 25°C, f = 1 MHz,	5	8	9	pF
			VDD = 3.3V.
	CCLK	Clock Input Capacitance	VDD = 3.3V.	5	8	9	pF
			VDDQ = 2.5V
	CIO	Input/Output Capacitance	VDDQ = 2.5V	5	8	9	pF
	CIO	Input/Output Capacitance		5	8	9	pF

Thermal Resistance [19]

	Parameter	Description	Test Conditions	100 TQFP	119 BGA	165 FBGA	Unit
	Parameter	Description	Test Conditions	Package	Package	Package	Unit
				Package	Package	Package
	ΘJA	Thermal Resistance	Test conditions follow standard	28.66	23.8	20.7	°C/W
		(Junction to Ambient)	test methods and procedures
			for measuring thermal
	ΘJC	Thermal Resistance	for measuring thermal	4.08	6.2	4.0	°C/W
	ΘJC	Thermal Resistance	impedance, in accordance with	4.08	6.2	4.0	°C/W
		(Junction to Case)	EIA/JESD51.
			EIA/JESD51.

Document #: 38-05543 Rev. *F

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Cypress CY7C1380F, CY7C1380D, CY7C1382F, CY7C1382D manual Capacitance, Thermal Resistance, Package, EIA/JESD51

Contents

Features Functional DescriptionSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1380D/CY7C1380F 3 512K x Logic Block Diagram CY7C1382D/CY7C1382F 3 1M xPin Configurations Pin Tqfp Pinout 3-Chip EnableBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Power supply inputs to the core of the device Power supply for the I/O circuitryPin Definitions Name Description Ground for the core of the deviceTCK Jtag Pin DefinitionsTMS Single Write Accesses Initiated by Adsp Single Read AccessesSingle Write Accesses Initiated by Adsc Functional OverviewSleep Mode Burst SequencesAddress A1 A0 Parameter Description Test Conditions MinTruth Table Operation Add. UsedFunction CY7C1382D/CY7C1382F Truth Table for Read/Write 4Function CY7C1380D/CY7C1380F Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Bypass RegisterTAP Timing ReservedParameter Description Min ClockTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA10 B10 P10 Electrical Characteristics Over the Operating Range Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistancePackage EIA/JESD51AC Test Loads and Waveforms 3V I/O Test Load 5V I/O Test LoadOutput Times Switching Characteristics Over the Operating Range 20Setup Times Switching Waveforms Read Cycle TimingWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Package Diagrams Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Submission Orig. Description of Change DateUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions