Cypress CY7C1380F, CY7C1380D, CY7C1382F, CY7C1382D specification

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Package Diagrams (continued)

Figure 16. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

15.00±0.10

A

0.25 C

15.00±0.10

A

0.3600.25.3±0C .05

TOP VIEW

							TOP VIEW
	PIN 1 CORNER
		PIN 1 CORNER
	1	2	3	4	5	6	7	8	9	10	11
A		1		2	3	4	5	6	7	8	9	10	11
B	A
B	A

CB

DC

ED

FE

GF

HG

JH

KJ

LK

ML

NM

PN

RP R

B	13.00±0.10
B	13.00±0.10
0.53±0.05	1.40 MAX.	0.15 C 1.40 MAX.
C	SEATING PLANE
C	SEATING PLANE
	SEATING PLANE
0.36	C
0.36	0.35±0.06	0.35±0.06

15.00±0.10

A

0.15 C

					BOTTOM VIEW
							BOTTOM VIEWPIN 1 CORNER
											PIN 1 CORNER
							Ø0.05 M C
									Ø0.05 M C
							Ø0.25 M C A B
							Ø0.50		-0Ø0.06	.25 M C A B
							Ø0.50		(165X)
									+0.14		-0.06
		11	10	9	8	7	6	5	Ø0.50		-0.06	(165X)
		11	10	9	8	7	6	5	4	3	2	1
											+0.14
				11	10	9	8	7	6	5	4	3	2	1A
														B	A
	1.00													C	B
		1.00												C
		1.00												D	C
														D	C
														E	D
														E
														F	E
														G	F
14.00														G
14.00														H	G
15.00±0.10	14.00													H
15.00±0.10	14.00													J	H
														K	J
														K
	7.00	7.00												L	K
	7.00	7.00												M	L
														M
														N	M
														N
														P	N
														P
														R	P
														R
															R
				5.00					1.00
A				5.00							1.00
A						5.00					1.00
						5.00
						10.00
								10.00
	B				13.00±0.10
		B					13.00±0.10
	0.15(4X)
		0.15(4X)
		NOTES :

SOLDERNOTESPAD TYPE: : NON-SOLDER MASK DEFINED (NSMD)

PACKAGESOLDERW IGHTPAD: 0TYPE.475g: NON-SOLDER MASK DEFINED (NSMD)

JEDEC REFERENCEPACKAGE WEIGHT: MO-216: 0./475gDESIGN 4.6C

PACKAGEJEDECODEREFERENCE: BB0AC : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

51-85180-*A

Document #: 38-05543 Rev. *F

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Cypress CY7C1380F, CY7C1380D, CY7C1382F, CY7C1382D manual Soldernotespad Type NON-SOLDER Mask Defined Nsmd

Contents

Features Functional DescriptionSelection Guide Description 250 MHz 200 MHz 167 MHz Unit Logic Block Diagram CY7C1380D/CY7C1380F 3 512K x Logic Block Diagram CY7C1382D/CY7C1382F 3 1M x Pin Configurations Pin Tqfp Pinout 3-Chip Enable Ball BGA Pinout Ball Fbga Pinout 3-Chip Enable Power supply inputs to the core of the device Power supply for the I/O circuitryPin Definitions Name Description Ground for the core of the device TCK Jtag Pin DefinitionsTMS Single Write Accesses Initiated by Adsp Single Read AccessesSingle Write Accesses Initiated by Adsc Functional Overview Sleep Mode Burst SequencesAddress A1 A0 Parameter Description Test Conditions Min Truth Table Operation Add. Used Function CY7C1382D/CY7C1382F Truth Table for Read/Write 4Function CY7C1380D/CY7C1380F Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Bypass Register TAP Timing ReservedParameter Description Min Clock TAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Test Conditions Min Identification Register Definitions Scan Register SizesIdentification Codes Register Name Bit Size Ball BGA Boundary Scan Order 14 Bit # Ball ID A10 B10 P10 Electrical Characteristics Over the Operating Range Maximum RatingsOperating Range Range Ambient Capacitance Thermal ResistancePackage EIA/JESD51 AC Test Loads and Waveforms 3V I/O Test Load 5V I/O Test Load Output Times Switching Characteristics Over the Operating Range 20Setup Times Switching Waveforms Read Cycle Timing Write Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Package Diagrams Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Submission Orig. Description of Change Date USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions