Cypress CY7C1382F, CY7C1380F Switching Characteristics Over the Operating Range 20, Output Times

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Switching Characteristics Over the Operating Range [20, 21]

	Description	250 MHz		200 MHz		167 MHz		Unit
Parameter		Min	Max	Min	Max	Min	Max
t	V (Typical) to the first Access [22]	1		1		1		ms
POWER	DD

Clock

tCYC	Clock Cycle Time	4.0	5	6
tCH	Clock HIGH	1.7	2.0	2.2
tCL	Clock LOW	1.7	2.0	2.2
Output Times

ns

ns

ns

tCO

tDOH

tCLZ

tCHZ

tOEV

tOELZ

tOEHZ

Data Output Valid After CLK Rise			2.6		3.0		3.4	ns
Data Output Hold After CLK Rise		1.0		1.3		1.3		ns
Clock to Low-Z [23, 24, 25]		1.0		1.3		1.3		ns
Clock to High-Z [23, 24, 25]			2.6		3.0		3.4	ns
	LOW to Output Valid		2.6		3.0		3.4	ns
OE
	LOW to Output Low-Z [23, 24, 25]	0		0		0		ns
OE
	HIGH to Output High-Z [23, 24, 25]		2.6		3.0		3.4	ns
OE

Setup Times

tAS	Address Setup Before CLK Rise						1.2	1.4	1.5
tADS	ADSC,		ADSP		Setup Before CLK Rise		1.2	1.4	1.5
tADVS		Setup Before CLK Rise					1.2	1.4	1.5
	ADV
tWES	GW,	BWE,		BW		X Setup Before CLK Rise	1.2	1.4	1.5
tDS	Data Input Setup Before CLK Rise						1.2	1.4	1.5
tCES	Chip Enable SetUp Before CLK Rise						1.2	1.4	1.5
Hold Times

ns

ns

ns

ns

ns

ns

tAH

tADH

tADVH

tWEH

tDH

tCEH

Address Hold After CLK Rise						0.3	0.4	0.5
ADSP,		ADSC		Hold After CLK Rise		0.3	0.4	0.5
ADV	Hold After CLK Rise					0.3	0.4	0.5
					X Hold After CLK Rise	0.3	0.4	0.5
GW,	BWE,		BW
Data Input Hold After CLK Rise						0.3	0.4	0.5
Chip Enable Hold After CLK Rise						0.3	0.4	0.5

ns

ns

ns

ns

ns

ns

Notes

20.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

21.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

22.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated.

23.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ± 200 mV from steady-state voltage.

24.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

25.This parameter is sampled and not 100% tested.

Document #: 38-05543 Rev. *F Page 22 of 34

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