Pin Definitions, Tms, TCK Jtag | Cypress CY7C1382D, CY7C1380F

				CY7C1380D, CY7C1382D
				CY7C1380F, CY7C1382F


Table 1. Pin Definitions (continued)

MODE	Input-Static	Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left
		floating selects interleaved burst sequence. This is a strap pin and must remain static during
		device operation. Mode pin has an internal pull up.

TDO	JTAG serial	Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
	output	feature is not being utilized, this pin must be disconnected. This pin is not available on TQFP
	Synchronous	packages.

TDI	JTAG serial	Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
	input	not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on
	Synchronous	TQFP packages.
TMS	JTAG serial	Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
	input	not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on
	Synchronous	TQFP packages.

TCK	JTAG-	Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
	Clock	connected to VSS. This pin is not available on TQFP packages.
NC	–	No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not
		internally connected to the die.

Document #: 38-05543 Rev. *F

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Cypress CY7C1382D, CY7C1380F, CY7C1380D, CY7C1382F manual Pin Definitions, Tms, TCK Jtag

Contents

Description 250 MHz 200 MHz 167 MHz Unit FeaturesFunctional Description Selection Guide Logic Block Diagram CY7C1382D/CY7C1382F 3 1M x Logic Block Diagram CY7C1380D/CY7C1380F 3 512K x Pin Tqfp Pinout 3-Chip Enable Pin Configurations Ball BGA Pinout Ball Fbga Pinout 3-Chip Enable Ground for the core of the device Power supply inputs to the core of the devicePower supply for the I/O circuitry Pin Definitions Name Description TMS Pin DefinitionsTCK Jtag Functional Overview Single Write Accesses Initiated by AdspSingle Read Accesses Single Write Accesses Initiated by Adsc A1 A0 Parameter Description Test Conditions Min Sleep ModeBurst Sequences Address Operation Add. Used Truth Table Function CY7C1380D/CY7C1380F Truth Table for Read/Write 4Function CY7C1382D/CY7C1382F TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction Set Clock TAP TimingReserved Parameter Description Min Parameter Description Test Conditions Min TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test Conditions Register Name Bit Size Identification Register DefinitionsScan Register Sizes Identification Codes Bit # Ball ID Ball BGA Boundary Scan Order 14 A10 B10 P10 Range Ambient Electrical Characteristics Over the Operating RangeMaximum Ratings Operating Range EIA/JESD51 CapacitanceThermal Resistance Package 5V I/O Test Load AC Test Loads and Waveforms 3V I/O Test Load Setup Times Switching Characteristics Over the Operating Range 20Output Times Read Cycle Timing Switching Waveforms Write Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Package Diagrams Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Submission Orig. Description of Change Date Document History Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB