Cypress CY7C1380D, CY7C1380F, CY7C1382D, CY7C1382F - page 7

CY7C1380D, CY7C1382DCY7C1380F, CY7C1382F

Document #: 38-05543 Rev. *F Page 7 of 34

MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left

floating selects interleaved burst sequence. This is a strap pin and must remain static during

device operation. Mode pin has an internal pull up.

TDO JTAG serial

output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG

feature is not being utilized, this pin must be disconnected. This pin is not available on TQFP

packages.

TDI JTAG serial

input

Synchronous

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is

not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on

TQFP packages.

TMS JTAG serial

input

Synchronous

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is

not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on

TQFP packages.

TCK JTAG-

Clock

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be

connected to VSS. This pin is not available on TQFP packages.

NC – No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not

internally connected to the die.

Table 1. Pin Definitions (continued)

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Contents

Main CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Features Functional Description Selection Guide CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Logic Block Diagram CY7C1380D/CY7C1380F [3] (512K x 36) WRITE DRIVER GW CE Page 119-Ball BGA Pinout 165-Ball FBGA Pinout (3-Chip Enable) 2345671 A B C D E F G H J K L M N P R 891011 2345671 A B C D E F G H J K L M N P R 891011 Page Page CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Functional Overview Single Read Accesses Single Write Accesses Initiated by ADSP Single Write Accesses Initiated by ADSC Burst Sequences Sleep Mode Truth Table Truth Table for Read/Write IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature TAP Controller State Diagram Test Access Port (TAP) TAP Controller Block Diagram CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F TAP Instruction Set Reserved TAP Ti min g TAP AC Switching Characteristics Over the Operating Range [10, 11] 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions Identification Register Definitions Scan Register Sizes Identification Codes 119-Ball BGA Boundary Scan Order[14, 15] 165-Ball BGA Boundary Scan Order [14, 16] Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance Figure 9. AC Test Loads and Waveforms = 1.5V (c) (a) (b) V Switching Characteristics Switching Waveforms Figure 10. Read Cycle Timing Figure 11. Write Cycle Timing 27.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Figure 12. Read/Write Cycle Timing Figure 13. ZZ Mode Timing Ordering Information Page Page Package Diagrams Figure 14. 100-Pin Thin Plastic Quad Flat Pack (14 x 20 x 1.4 mm) (51-85050) A Page Figure 16. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) Package Diagrams SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40 MAX. 51-85180-*A SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions