Cypress CY7C1380D, CY7C1380F, CY7C1382D, CY7C1382F TAP Ti min g, TAP AC Switching Characteristics Over the Operating Range [10, 11]

CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Document #: 38-05543 Rev. *F Page 14 of 34
when the EXTEST is entered as the current instruction. When
HIGH, it enables the output buffers to drive the output bus. When
LOW, this bit places the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Ti min g
TAP AC Switching Characteristics Over the Operating Range [10, 11]
Parameter Description Min Max Unit
Clock
tTCYC TCK Clock Cycle Time 50 ns
tTF TCK Clock Frequency 20 MHz
tTH TCK Clock HIGH time 20 ns
tTL TCK Clock LOW time 20 ns
Output Times
tTDOV TCK Clock LOW to TDO Valid 10 ns
tTDOX TCK Clock LOW to TDO Invalid 0 ns
Setup Times
tTMSS TMS Setup to TCK Clock Rise 5 ns
tTDIS TDI Setup to TCK Clock Rise 5 ns
tCS Capture Setup to TCK Rise 5 ns
Hold Times
tTMSH TMS Hold after TCK Clock Rise 5 ns
tTDIH TDI Hold after Clock Rise 5 ns
tCH Capture Hold after Clock Rise 5 ns
tTL
Test Clock
(TCK)
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH tTMSS
tTDIH tTDIS
tTDOX
tTDOV
DON’T CARE UNDEFINED
Notes
10.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
11.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1ns.
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