Write Cycle Timing 26 | Cypress CY7C1380F, CY7C1380D, CY7C1382F

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Switching Waveforms (continued)

Figure 11. Write Cycle Timing [26, 27]

t CYC

CLK

tCH

tCL

tADS

tADH

ADSP

tADS

tADH

ADSC extends burst

tADS

tADH

ADSC

tAS

tAH

ADDRESS

A1

A2

A3

Byte write signals are

ignored for ﬁrst cycle when

tWES

tWEH

ADSP initiates burst

BWE,

BW X

tWES tWEH

GW

tCES

tCEH

CE

tADVS

tADVH

ADV

ADV suspends burst

OE

tDS

tDH

Data In (D)

High-Z

t

D(A1)

D(A2)

D(A2 + 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

OEHZ

ata Out (Q)

BURST READ

Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE

UNDEFINED

Note

27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

Document #: 38-05543 Rev. *F

Page 24 of 34

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Cypress CY7C1380F, CY7C1380D, CY7C1382F, CY7C1382D manual Write Cycle Timing 26

Contents

Features Functional DescriptionSelection Guide Description 250 MHz 200 MHz 167 MHz Unit Logic Block Diagram CY7C1380D/CY7C1380F 3 512K x Logic Block Diagram CY7C1382D/CY7C1382F 3 1M x Pin Configurations Pin Tqfp Pinout 3-Chip Enable Ball BGA Pinout Ball Fbga Pinout 3-Chip Enable Power supply inputs to the core of the device Power supply for the I/O circuitryPin Definitions Name Description Ground for the core of the device Pin Definitions TMSTCK Jtag Single Write Accesses Initiated by Adsp Single Read AccessesSingle Write Accesses Initiated by Adsc Functional Overview Sleep Mode Burst SequencesAddress A1 A0 Parameter Description Test Conditions Min Truth Table Operation Add. Used Truth Table for Read/Write 4 Function CY7C1380D/CY7C1380FFunction CY7C1382D/CY7C1382F TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass Register TAP Timing ReservedParameter Description Min Clock TAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Test Conditions Min Identification Register Definitions Scan Register SizesIdentification Codes Register Name Bit Size Ball BGA Boundary Scan Order 14 Bit # Ball ID A10 B10 P10 Electrical Characteristics Over the Operating Range Maximum RatingsOperating Range Range Ambient Capacitance Thermal ResistancePackage EIA/JESD51 AC Test Loads and Waveforms 3V I/O Test Load 5V I/O Test Load Switching Characteristics Over the Operating Range 20 Setup TimesOutput Times Switching Waveforms Read Cycle Timing Write Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Package Diagrams Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Submission Orig. Description of Change Date Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB