Cypress CY7C1380D, CY7C1380F, CY7C1382D, CY7C1382F - page 29

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Document #: 38-05543 Rev. *F Page 29 of 34

Speed

(MHz) Ordering Code

Package

Diagram Part and Package Type Operating

Range

167 CY7C1380D-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1382D-167AXC

CY7C1380F-167AXC

CY7C1382F-167AXC

CY7C1380F-167BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1382F-167BGC

CY7C1380F-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1382F-167BGXC

CY7C1380D-167BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1382D-167BZC

CY7C1380F-167BZC

CY7C1382F-167BZC

CY7C1380D-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1382D-167BZXC

CY7C1380F-167BZXC

CY7C1382F-167BZXC

CY7C1380D-167AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial

CY7C1382D-167AXI

CY7C1380F-167AXI

CY7C1382F-167AXI

CY7C1380F-167BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1382F-167BGI

CY7C1380F-167BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1382F-167BGXI

CY7C1380D-167BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1382D-167BZI

CY7C1380F-167BZI

CY7C1382F-167BZI

CY7C1380D-167BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1382D-167BZXI

CY7C1380F-167BZXI

CY7C1382F-167BZXI

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Contents

Main CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Features Functional Description Selection Guide CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Logic Block Diagram CY7C1380D/CY7C1380F [3] (512K x 36) WRITE DRIVER GW CE Page 119-Ball BGA Pinout 165-Ball FBGA Pinout (3-Chip Enable) 2345671 A B C D E F G H J K L M N P R 891011 2345671 A B C D E F G H J K L M N P R 891011 Page Page CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Functional Overview Single Read Accesses Single Write Accesses Initiated by ADSP Single Write Accesses Initiated by ADSC Burst Sequences Sleep Mode Truth Table Truth Table for Read/Write IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature TAP Controller State Diagram Test Access Port (TAP) TAP Controller Block Diagram CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F TAP Instruction Set Reserved TAP Ti min g TAP AC Switching Characteristics Over the Operating Range [10, 11] 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions Identification Register Definitions Scan Register Sizes Identification Codes 119-Ball BGA Boundary Scan Order[14, 15] 165-Ball BGA Boundary Scan Order [14, 16] Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance Figure 9. AC Test Loads and Waveforms = 1.5V (c) (a) (b) V Switching Characteristics Switching Waveforms Figure 10. Read Cycle Timing Figure 11. Write Cycle Timing 27.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Figure 12. Read/Write Cycle Timing Figure 13. ZZ Mode Timing Ordering Information Page Page Package Diagrams Figure 14. 100-Pin Thin Plastic Quad Flat Pack (14 x 20 x 1.4 mm) (51-85050) A Page Figure 16. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) Package Diagrams SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40 MAX. 51-85180-*A SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions