Intel Microcontroller, 80C196NU, 8XC196NP manual Rot, Capture Mode on, Compare Mode RT

EVENT PROCESSOR ARRAY (EPA)

EPAx_CON (Continued)	Address:	Table 10-2 on page 10-3
x = 0–3	Reset State:	00H

The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the others can be addressed as bytes.

x = 1, 3

x = 0, 2

15

—	—	—	—
7
TB	CE	M1	M0
7
TB	CE	M1	M0

8

— — — RM

0

RE — ROT ON/RT

0

RE — ROT ON/RT

Bit	Bit		Function
Number	Mnemonic
1	ROT	Reset Opposite Timer
		Controls different functions for capture and compare modes.
		In Capture Mode:
		0	= causes no action
		1	= resets the opposite timer
		In Compare Mode:
		Selects the timer that is to be reset if the RT bit is set.
		0	= selects the reference timer for possible reset
		1	= selects the opposite timer for possible reset
		The TB bit (bit 7) selects which is the reference timer and which is the
		opposite timer.
0	ON/RT	Overwrite New/Reset Timer
		The ON/RT bit functions as overwrite new in capture mode and reset
		timer in compare mode.
		In Capture Mode (ON):
		An overrun error is generated when an input capture occurs while the
		event-time register (EPAx_TIME) and its buffer are both full. When an
		overrun occurs, the ON bit determines whether old data is overwritten or
		new data is ignored:
		0	= ignores new data
		1	= overwrites old data in the buffer
		In Compare Mode (RT):
		0	= disables the reset function
		1	= resets the ROT-selected timer

†These bits apply to the EPA1_CON and EPA3_CON registers only.

Figure 10-10. EPA Control (EPAx_CON) Registers (Continued)

10-21