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Intel manual Deferred Bus-cycle Mode 80C196NU Only, Demultiplexed System Bus Timing 80C196NU

Models: Microcontroller 80C196NU 8XC196NP

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8XC196NP, 80C196NU USER’S MANUAL
TCHCL	TCLCL		T
TCLLH	TLLCH		TCHWH
CLKOUT
			TLHLH
			TWHLH
			TRHLH	TLHLL
ALE
			TRHRL
TRLCL			TRHDZ
T	T	RLRH	TRHAX
AVRL		RLRH
RD#
		TCHDV
	TRLDV
TAVDV
TSLDV
AD15:0			Valid
(read)			Valid
(read)
TWLCL			TWHQX
TAVWL	TWLWH		TWHAX
WR#
AD15:0	TQVWH
AD15:0			Valid
(write)			Valid
(write)
			TWHBX,TRHBX
BHE#, INST
A19:0
CSx#
				T0012-02

Figure 13-23. Demultiplexed System Bus Timing (80C196NU)

13.9.1 Deferred Bus-cycle Mode (80C196NU Only)

The 80C196NU offers a deferred bus cycle mode. This bus mode (enabled by CCR1.5; see Figure 13-7 on page 13-16) reduces bus contention when using the 80C196NU in demultiplexed mode with slow memories. As shown in Figure 13-24, a delay of 2t occurs in the first bus cycle follow- ing a chip-select output change and the first write cycle following a read cycle.

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Intel 8XC196NP, Microcontroller manual Deferred Bus-cycle Mode 80C196NU Only, Demultiplexed System Bus Timing 80C196NU

Contents

8XC196NP, 80C196NU Microcontroller User’ Manual 8XC196NP, 80C196NU Microcontroller User’s Manual Intel Corporation Contents Chapter Programming Considerations Contents Chapter Ports EPA Functional Overview Programming the Serial Port8XC196NP, 80C196NU USER’S Manual Chapter Interfacing with External Memory Appendix C Registers Glossary Index Figures 10-7 Valid EPA Input Events 13-16 Tables 10-5 Example Control Register Settings and EPA Operations 8XC196NP and 80C196NU Signals Arranged by Function Guide to This Manual Page Chapter Guide to this Manual Manual Contents8XC196NP, 80C196NU USER’S Manual Addresses Notational Conventions and TerminologyItalics Related Documents Units of measureHandbooks and Product Information Application Notes, Application Briefs, and Article ReprintsTitle Order Number MCS 96 Microcontroller Datasheets Automotive MCS 96 Microcontroller Datasheets Commercial/Express8XC196NP, 80C196NU USER’S Manual Intentionally Left Blank Intentionally Left Blank World Wide Web Technical SupportProduct Literature Page Architectural Overview Page Typical Applications Chapter Architectural OverviewBlock Diagram Device FeaturesFeatures of the 8XC196NP and 80C196NU ROMRegister File CPU ControlCode Execution Register Arithmetic-logic Unit RaluInstruction Format Memory ControllerMultiply-accumulate 80C196NU Only Interrupt ServiceClock Circuitry 8XC196NP Internal TimingClock Circuitry 80C196NU 12.5 MHz State Times at Various Frequencies25 MHz 50 MHzMultiplier State Time PLLEN21Internal Peripherals Event Processor Array EPA and Timer/Counters1 I/O Ports Serial I/O SIO PortReducing Power Consumption Pulse-width Modulator PWMSpecial Operating Modes Design Considerations for 80C196NP to 80C196NU Conversions Testing the Printed Circuit Board8XC196NP, 80C196NU USER’S Manual Advanced Math Features Page Enhanced Multiplication Instructions Chapter Advanced Math FeaturesOperating Modes Saturation ModeMultiply/Accumulate Example Code Instructions Execution TimeFractional Mode Accumulator Register ACC0x Accumulator Control and Status Register Accstat AccstatBit Function Number Mnemonic Effect of SME and FME Bit Combinations SME FMEDescription Programming Considerations Page Operand Type Definitions Overview of the Instruction SETOperand Type No. Signed Possible Values Addressing RestrictionsBIT Operands Byte OperandsSHORT-INTEGER Operands Word Operands Integer OperandsDOUBLE-WORD Operands QUAD-WORD Operands LONG-INTEGER OperandsConverting Operands Conditional JumpsExtended Instructions Floating Point OperationsAddressing Modes ESTImmediate Addressing Direct AddressingIndirect Addressing Definition of Temporary RegistersExtended Indirect Addressing Indirect Addressing with AutoincrementExtended Indirect Addressing with Autoincrement Indirect Addressing with the Stack Pointer Indexed AddressingShort-indexed Addressing Long-indexed AddressingExtended Indexed Addressing Zero-indexed AddressingExtended Zero-indexed Addressing Extended Addressing Assembly Language Addressing Mode SelectionsDesign Considerations for 1-MBYTE Devices Software Standards and ConventionsUsing Registers Addressing 32-bit OperandsAddressing 64-bit Operands Linking Subroutines Software Protection Features and Guidelines Memory Partitions Page Memory MAP Overview Chapter Memory PartitionsF0H FFH 2FH 1FH 0FH F1HMemory Partitions FFH80C196NP/NU External 83C196NP ROM Hex Description Addressing Modes XC196NP and 80C196NU Memory MapExternal Memory Program Memory Access for the 83C196NPProgram and Special-purpose Memory Program Memory in Page FFHSpecial-purpose Memory Access for the 83C196NP Special-purpose MemoryXC196NP and 80C196NU Special-purpose Memory Addresses Peripheral Special-function Registers SFRs Chip Configuration BytesReserved Memory Locations Interrupt and PTS VectorsPeripheral SFRs 1F7CH 1F7EH1F7AH 1F4EHCPU SFRs Stack PointerGeneral-purpose Register RAM Register File Memory AddressesStack Pointer SP Address Description Addressing Modes RangeCPU SFRs CPU Special-function Registers SFRs8XC196NP CPU SFRs Address High Odd Byte Low Even Byte 80C196NU CPU SFRs Address High Odd Byte Low Even Byte8XC196NP WindowingWSR Selecting a WindowHlden Bit FunctionSelecting a Window of the Upper Register File Addressing a Location Through a Window Base WSR or WSR1 Value WSR Value for 10. WindowsPeripheral SFRs Upper Register File2.1 32-byte Windowing Example 11. Windowed Base Addresses2.2 64-byte Windowing Example 2.3 128-byte Windowing ExampleUnsupported Locations Windowing Example 8XC196NP Only Using the Linker Locator to Set Up a WindowType Base Length Alignment Windowing and Addressing Modes This listing shows the disassembled codeRemapping Internal ROM 83C196NP only Fetching Code and Data in the 1-MBYTE and 64-KBYTE Modes Accessing DataFetching Instructions EpcpcFormation of Extended and Nonextended Addresses Code Fetches in the 64-Kbyte Mode Code Fetches in the 1-Mbyte Mode80C196NP and 80C196NU Data Fetches in the 1-Mbyte and 64-Kbyte ModesExample 1 Using the 64-Kbyte Mode Memory Configuration ExamplesRD# WR# CE#Address Description 12. Memory Map for the System in Figure80C196NP and 80C196NU External flash memory 80C196NP and 80C196NU UnimplementedRD# WR# CE# Example 2 a 64-Kbyte System with Additional Data StorageFfffffh D70 OE# WE# 02FFFFH80C196NP and 80C196NU External RAM 13. Memory Map for the System in FigureExample 3 Using 1-Mbyte Mode 01FFFFHOE# WE# OE# WRH# WRL# RD# 14. Memory Map for the System in Figure 80C196NP and 80C196NU External memoryFbffffh Standard and PTS Interrupts Page Overview of Interrupts Chapter Standard and PTS InterruptsFlow Diagram for PTS and Standard Interrupts Interrupt Signals and Registers Interrupt SignalsInterrupt and PTS Control and Status Registers Special Interrupts Interrupt Sources and PrioritiesIntpend PtsselInterrupt Sources, Vectors, and Priorities Interrupt Controller PTS ServiceUnimplemented Opcode Software TrapMultiplexed Interrupt Sources External Interrupt PinsEnd-of-PTS Interrupts 1.3 NMISituations that Increase Interrupt Latency Interrupt LatencyStandard Interrupt Latency Calculating LatencyStandard Interrupt Response Time PTS Interrupt Latency PTS Mode Execution Time in State Times Programming the InterruptsExecution Times for PTS Cycles Programming Considerations for Multiplexed Interrupts PtsselBit Mnemonic Interrupt PTS Vector Intmask EPA0 EXTINT1 EXTINT0 OVRTM2 OVRTM1Bit Mnemonic Interrupt Standard Vector INTMASK1 Modifying Interrupt PrioritiesNMI EXTINT3 EXTINT2 EPA3 EPA2 EPA1RET Cseg AT 0FF200CH Determining the Source of an Interrupt Intpend Interrupt Pending Intpend RegisterINTPEND1 Initializing the PTS Control BlocksPWM Remap Mode PWM Toggle ModeSpecifying the PTS Count Single TransferSelecting the PTS Mode PtssrvEPA3 EPA2 EPA1 EXTINT0 OVRTM1 OVRTM2 Single Transfer Mode PtsconAddress Ptspcb + Ptsdst HI Ptsdst LO Ptssrc HI Ptssrc LO Ptscon Ptscount PTS Single Transfer Mode Control BlockRegister Location Function Ptsdst Ptscb +8XC196NP, 80C196NU USER’S Manual Single Transfer Mode Ptscb Block Transfer ModeBlock Transfer Mode Ptscb Ptscount = 09HPtsblock Ptscb + PTS Block Transfer Mode Control BlockIncrement the contents of Ptssrc after each byte or word PWM Modes PWM Toggle Mode PWM Remap ModeComparison of PWM Modes PTSCONST214. a Generic PWM Waveform PWM Toggle Mode ExamplePTSCONST1 HI = T1 HI PTSCONST1 LO = T1 LO PTSPTR1 HI = 1FH PWM Toggle Mode PtscbPTSCONST2 L PTSCONST2 HPTSCONST1 H PTSCONST1 LTmod Ptscon Ptscb +16. EPA and PTS Operations for the PWM Toggle Mode Example PWM Remap Mode Example PWM Remap Mode Ptscb PTSCONST1 HI PTSCONST1 LO PTSPTR1 HI PTSPTR1 LO Ptscon PTS PWM Remap Mode Control BlockPWM Tmod PTS PWM Remap Mode Control Block Register18. EPA and PTS Operations for the PWM Remap Mode Example Ports Page Bidirectional Ports I/O Ports OverviewDevice I/O Ports Port Bits TypePort Pin Special-function Associated Signals Bidirectional Port PinsBidirectional Port Control and Status Registers Bidirectional Port Operation8XC196NP, 80C196NU USER’S Manual Bidirectional Port Structure Sfdir Logic Table for Bidirectional Ports in I/O ModeBidirectional Port Pin Configurations Bidirectional Port Pin Configuration Example Control Register Values for Each ConfigurationPort Configuration Example HZ1 Bidirectional Port ConsiderationsP2.7/CLKOUT Port Pin Extended-address Signal Type Eport PinsDesign Considerations for External Interrupt Inputs Eport10. Eport Control and Status Registers Eport OperationEport Block Diagram Output Enable ResetComplementary Output Mode Open-drain Output ModeEport Structure 11. Logic Table for Eport in I/O Mode Input Mode12. Logic Table for Eport in Address Mode Epmode Epdir EpregConfiguring Eport Pins for Extended-address Functions Configuring Eport PinsConfiguring Eport Pins for I/O 13. Configuration Register Settings for Eport PinsEport Status During Instruction Execution Eport ConsiderationsDesign Considerations Page Serial I/O SIO Port Page Serial I/O SIO Port Functional Overview SIO Block DiagramSerial Port Signals Serial I/O Port Signals and RegistersSerial Port Control and Status Registers SerialSbufrx 1FB8H P1REG 1FD4HSbuftx 1FBAH Spbaud 1FBCH,1FBDHSynchronous Mode Mode Serial Port ModesSpstatus 1FB9H Asynchronous Modes Modes 1, 2, Mode 0 TimingMode Serial Port Frames for ModeMode 2 and 3 Timings Serial Port Frames in Mode 2Programming the Serial Port Configuring the Serial Port PinsProgramming the Control Register Programming the Baud Rate and Clock SourceSpcon PAR TB8 PRS REN PENPAR Bit Function SpconSpbaud Spbaud Values When Using the Internal Clock at 25 MHz Baud Rate Spbaud Register Value Note Error Mode Mode 1, 28A2BH Enabling the Serial Port Interrupts Baud Rate Spbaud Register Value † Error ModeDetermining Serial Port Status 8A2CHSpstatus RPE/RB8 TXERPE/RB8 Serial I/O SIO Port Page Pulse-width Modulator Page PWM Functional Overview PWM Block Diagram 8XC196NP OnlyPWM Signals PWM Signals and RegistersPWM Control and Status Registers PWM Operation8XC196NP, 80C196NU USER’S Manual Programming the Frequency and Period EnabledE6H FFHPWM Output Frequencies 80C196NU PWM Output Frequencies 8XC196NPCLK0 CLK1 CLK0CONREG0 Programming the Duty CycleFEH CLK1 CLK0Clock Prescaler DisabledPWM xCONTROL Address PWM Duty CycleSample Calculations PWM Output Alternate Port Function PWM Output Enabled WhenEnabling the PWM Outputs PWM Output Alternate FunctionsD/A Buffer Block Diagram Event Processor Array EPA Page EPA Functional Overview Chapter Event Processor Array EPAEPA and Timer/Counter Signals EPA and TIMER/COUNTER Signals and RegistersPort Pin EPA Signals EPAEPA Control and Status Registers TIMER2 TIMER1EPA Timer/Counters TIMER/COUNTER Functional OverviewQuadrature Clocking Mode Cascade Mode Timer 2 OnlyQuadrature Mode Interface Quadrature Mode Truth Table EPA Channel Functional Overview Quadrature Mode Timing and CountA Single EPA Capture/Compare Channel Operating in Capture ModeEPA Simplified Input-capture Structure Action taken when a valid edge occurs Action Taken when a Valid Edge OccursEPA Overruns EPAxCON.0Operating in Compare Mode Preventing EPA OverrunsGenerating a Low-speed PWM Output Generating a Medium-speed PWM Output Generating a High-speed PWM Output Configuring the EPA and Timer/Counter Port Pins Programming the EPA and TIMER/COUNTERSProgramming the Timers Generating the Highest-speed PWM OutputPrescaler Divisor Resolution † T1CONTROLClock Source Direction Source T2CONTROL Prescaler Resolution †Example Control Register Settings and EPA Operations Mode ROT ON/RTProgramming the Capture/Compare Channels EPA xCON Address Reset State 00H = 1 = 0ROT ON/RT Compare Mode Action Capture Mode EventCapture Mode on Compare Mode RTROT Enabling the EPA Interrupts Determining Event StatusEpamask Epapend † 12. EPA Interrupt Pending Epapend RegisterProgramming Examples for EPA Channels EPA Capture Event Program Unsigned char Unused Ptscon EPA PWM Output Program10-27 Page Minimum Hardware Considerations Page Minimum Required Signals SignalMinimum Connections Port Where to Find Configuration Information I/O Port Configuration GuideUnused Inputs 11.1.2 I/O Port Pin ConnectionsMinimum Hardware Connections Noise Protection Tips Applying and Removing PowerOn-chip Oscillator Circuit ON-CHIP Oscillator CircuitryExternal Crystal Connections External Clock Connections Using AN External Clock SourceReset Timing Sequence Resetting the DeviceInternal Reset Circuitry Generating an External ResetMinimum Reset Circuit Issuing an Illegal Idlpd Key Operand Issuing the Reset RST InstructionPage Special Operating Modes Page Operating Mode Control Signals Special Operating Mode Signals and RegistersPort Pin Signal Type Description Name OncePort Pin Signal Type Description Operating Mode Control and Status RegistersPLLEN21 CCR0P2DIR 1FD3H Reducing Power ConsumptionP2MODE 1FD1H P2REG 1FD5HClock Control During Power-saving Modes 8XC196NP Clock Control During Power-saving Modes 80C196NU Idle ModeStandby Mode 80C196NU only Enabling and Disabling Standby ModeEntering Standby Mode Powerdown Mode Exiting Standby ModeEnabling and Disabling Powerdown Mode Entering Powerdown ModeExiting Powerdown Mode Generating a Hardware ResetAsserting an External Interrupt Signal External RC Circuit Selecting C1 Typical Voltage on the RPD Pin While Exiting Powerdown Reserved Test Modes 80C196NU only Once ModePLLEN2 PLLEN1 C196NU Clock ModesPage Interfacing with External Memory Page Example of Internal and External Addresses Internal and External AddressesExternal Memory Interface Signals External Memory Interface SignalsBit Multiplexed Bus Mode Bit Demultiplexed ModeDescription Multiplexed With Bytes AccessedALE BHE#EA# Name Type Description Multiplexed WithInst ReadyCHIP-SELECT Unit WRL#WRH# Register Address Description Mnemonic Chip-select RegistersAddrcom Address Reset State Defining Chip-select Address RangesRegister Address Register Address Reset Value Addrmsk Address Reset StateBase Addresses for Several Sizes of the Address Range Address Mbyte Kbyte BytesFFB00H FFE00H FFD00H FFF00H Controlling Wait States, Bus Width, and Bus Multiplexing Buscon Address Reset StateWS1 WS0 Wait StatesBUSCONx Addresses and Reset Values Chip-select Unit Initial ConditionsInitializing the Chip-select Registers Example of a Chip-select Setup Sram Chip ContentsUart BusconChip Address Size Number Contents Chip Configuration Registers and Chip Configuration BytesResults for the Chip-select Example Addrcom AddrmskCCR0 WS1 WS0 Demux BHE#WS0 WS1 CCR1 Remap MODE64Remap 13-17 BUS Width and Multiplexing Bit Multiplexed Bus Bit Demultiplexed BusBit Demultiplexed Bus ALE ALEBit Multiplexed Bus 13.5.1 a 16-bit Example System CS# 13.5.2 16-bit Bus TimingsRD# Clkout ALE13.5.3 8-bit Bus Timings A190 Address AD158 High Address Comparison of Multiplexed and Demultiplexed Buses Wait States Ready ControlBus Description Demultiplexed Bus ns† Multiplexed Bus ns† Symbol Definition 11. Ready Signal Timing DefinitionsBHE#, Inst Ready ALE14. Ready Timing Diagram Demultiplexed Mode 8XC196NP BUS-HOLD Protocol 15. Ready Timing Diagram Demultiplexed Mode 80C196NU12. HOLD#, HLDA# Timing Definitions Symbol ParameterEnabling the Bus-hold Protocol Disabling the Bus-hold ProtocolHold Latency WRITE-CONTROL Modes Regaining Bus Control13. Maximum Hold Latency Bus Cycle TypeALE WR# WRL# 14. Write Signals for Standard and Write Strobe ModesBHE# WRH# Bus Word/Byte Standard Write Strobe18. Decoding WRL# and WRH# System BUS AC Timing Specifications RD# WRH# WRL#WE# OE# 20. Multiplexed System Bus Timing 8XC196NP 21. Multiplexed System Bus Timing 80C196NU 22. Demultiplexed System Bus Timing 8XC196NP 23. Demultiplexed System Bus Timing 80C196NU Deferred Bus-cycle Mode 80C196NU Only24. Deferred Bus-cycle Mode Timing Diagram 80C196NU 15. AC Timing Symbol Definitions Signals Explanation of AC SymbolsAC Timing Definitions ConditionsSymbol Definition 8XC196Nx Meets These Specifications 13-44 13-45 Page Instruction Set Reference Page Appendix a Instruction SET Reference Opcode Table A-1. Opcode Map Left HalfTable A-1. Opcode Map Right Half Mnemonic Description Table A-2. Processor Status Word PSW FlagsValue of Bits Shifted Off Instruction Quotient Stored Flag Set if Quotient isTable A-4. PSW Flag Setting Symbols Symbol DescriptionInstruction Jumps to Destination if Continues if Variable Description Table A-5. Operand VariablesTable A-6. Instruction Set PSW Flag SettingsMnemonic Operation C V VT STInstruction Format Dest ← Dest and SRCAndb PTRS, Cntreg BmovCount ← Count Mnemonic Operation Instruction FormatDest PC ← DestClear WORD. Clears the value Compare BYTES. Subtracts the source Dest MOD SRC DIVDjnz Decrement and Jump if not Zero ← Dest MOD SRCDjnzw Decrement and Jump if not Zero Dpts Disable Peripheral TransactionCount ← Cntreg Ebmovi Extended Interruptable Block PTRS, CntregDstptr ← Ptrs + Dstptr ← Srcptr Ptrs ← Srcptr + EBROnto the stack, then adds to the program ELD Epts Enable Peripheral TransactionEXT SIGN-EXTEND Integer Into Long SRC, DestExtb Extb SIGN-EXTEND SHORT-INTEGER IntoIncrement WORD. Increments the value Word operand by JGE Jump if Signed Greater than or Mnemonic Operation Instruction FormatJLE Jump if Signed Less than or Equal JGTNegative flag is set, this instruction adds JNV Jump if Overflow Flag is Clear JNHJnvt Jnvt Jump if OVERFLOW-TRAP Flag isJVT JVT Jump if OVERFLOW-TRAP Flag is SETMbyte mode Kbyte modeMulb MULMulu MuluMulub Dest ← Dest PSW Flag SettingsNEG Negate INTEGER. Negates the valueDest ← not Dest MnemonicORB Dest ← Dest or SRCPSW/INTMASK ← SP INTMASK1/WSR ← SPSP ← INTMASK1/WSR INTMASK1 ← SP ← PSW/INTMASK PSW/INTMASK ←Scall RSTWreg,#count SHR ShllRange of 0 to 31 1FH, inclusive. If Shral Shral Arithmetic Right Shift DoubleSkip Shrl Logical Right Shift DOUBLE-WORDSUB Rightmost operandSubc Subtract Words with Borrow DEST, SRC SubbSubc Subcb Subtract Bytes with Borrow DEST, SRCIndex and #MASK = Offset × Offset + Tbase = Dest PC ← Dest Tijmp TBASE, INDEX, #MASKSRC MnemonicDest ← Dest XOR SRC XORHex Code Instruction Mnemonic Table A-7. Instruction OpcodesClrb Notb Negb Decb Extb Incb Shrb Shlb ShrabHex Code Instruction SET Reference 8XC196NP, 80C196NU USER’S Manual ST Direct ELD Indirect Table A-8. Instruction Lengths and Hexadecimal Opcodes Arithmetic Group Direct Immediate Indirect Indexed MnemonicSubc Subcb Logical Direct Immediate Indirect Stack Direct Immediate Indirect Indexed Mnemonic Opcode LengthPOP Popa Popf Push Pusha Pushf Extended Data Direct ImmediateEbmovi ELD Eldb EST Estb Direct ImmediateEBR Ejmp Jump Direct ImmediateCall Direct Immediate Lcall RETJGE JGT JLE JLT JNC JNE JNH Jnst JNV Jnvt JST JVT Djnz Djnzw JBCLength Opcode Shift Mnemonic Direct Immediate Indirect IndexedSpecial Mnemonic Direct Immediate Indirect PTSArithmetic Group Indirect Table A-9. Instruction Execution Times in State TimesNormal Autoinc Short Long Reg Mem Mem RegMnemonic Direct Immed Normal Autoinc Short Long Reg Mem DIV Divb Divu DivubLogical Stack Register Indirect Normal Autoinc ShortReg Mem Extended-indexed Data Mnemonic Extended-indirect NormalIndexed Mnemonic Autoinc Short Long Reg MemLjmp Sjmp Tijmp Mnemonic Direct ImmedAutoinc Short Long Indirect Indexed Mnemonic Direct ImmedMnemonic Short-Indexed Conditional JumpShift Mnemonic DirectClrc Clrvt Idlpd Special Mnemonic Direct Immed Indirect IndexedNOP RST Setc Skip Immed Indirect IndexedPage Signal Descriptions Page Table B-1 XC196NP and 80C196NU Signals Arranged by Function Functional Groupings of SignalsX8XC196NP Figure B-1 XC196NP 100-lead Sqfp PackageFigure B-2 XC196NP 100-lead QFP Package X8XC196NU Figure B-3 C196NU 100-lead Sqfp PackageFigure B-4 C196NU 100-lead QFP Package Table B-3. Signal Descriptions Signal DescriptionsTable B-2. Description of Columns of Table B-3 Column Heading Description NameWRH# BREQ# Byte High Enable†EXTINT30 EPORT.30VSS HOLD#PLLEN1 PLLEN2 Name Type DescriptionVSS if either of the following conditions are true Asserted only during external memory writes Table B-4. Definition of Status Symbols Default ConditionsRESET# NP/NU RESET#WK1 EPORT.30 Ready WK1 RESET# RPDALE WK0 BHE# WK1Registers Page Table C-1. Modules and Related Registers Chip ConfigurationCPU EPA InterruptsTable C-2. Register Name, Address, and Reset Status EPA2TIME EPA3CONEPA3TIME 1FD6H Xxxx P1REGWSR1 NU Xxxx SpbaudTable C-3. ACC0x Addresses and Reset Values ACC0xACC0x Accstat AccstatSME FME Table C-4. Effect of SME and FME Bit CombinationsTable C-5. ADDRCOMx Addresses and Reset Values ADDRCOMxAddrcom Address Table C-6. ADDRMSKx Addresses and Reset Values ADDRMSKx Address Table C-6 Reset StateADDRMSKx Table C-7. BUSCONx Addresses and Reset Values BUSCONxBuscon Address CCR0 CCR0CCR1 CCR1CONREG0 CONREG0PIN3 PIN2 PIN1 PIN0 EpdirEpmode EpmodeXXH EppinX0H EpregEpamask EpamaskEpapend EpapendEPA xCON Address EPAxCONBit Function EPAxCON Address Table C-8Bit Function Number Register Address Reset Value Table C-8. EPAxCON Addresses and Reset ValuesEPAxTIME Table C-9. EPAxTIME Addresses and Reset ValuesIntmask IntmaskINTMASK1 FF203EH EXTINT3FF203CH EXTINT2 Intpend IntpendINTPEND1 INTPEND1Onesreg OnesregFfffh 150 One These bits are always equal to FfffhPxDIR Table C-10. PxDIR Addresses and Reset ValuesXDIR Address PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0Table C-11. PxMODE Addresses and Reset Values Table C-12. Special-function Signals for PortsPxMODE PxPIN Table C-13. PxPIN Addresses and Reset ValuesXPIN Address Bit NumberPxREG Table C-14. PxREG Addresses and Reset ValuesPxREG Address Table C-14 P1REG 1FD4H FFH P2REG 1FD5H P3REG 1FDCH P4REG 1FDDHPSW PSWPSE Bit Function Number Mnemonic PSWPtssel PtsselFF200AH EXTINT1 PtssrvPWMxCONTROL Table C-15. PWMxCONTROL Addresses and Reset ValuesSbufrx SbufrxData Received Sbuftx SbuftxData to Transmit Xxxxh Spbaud SpbaudMode 1, 2 Baud Rate Spbaud Register Value Note Error ModeSpcon SpconSpstatus T1CONTROL T1CONTROLT2CONTROL T2CONTROLTIMERx Table C-17. TIMERx Addresses and Reset ValuesTimer Address Byte Windows WSRRegister Memory 00E0-00FFH Mnemonic LocationRegister Memory 00E0-00FFH 00C0-00FFH TIMER2 † TIMER1 †P4DIR 1FDBH 7EH 00FBH 3FH 00DBH 1FH P4MODE 1FD9H PWM1CONTROL 1FB2H 7DHRegister Memory 0060-007FH 0040-007FH Mnemonic Location WSR10060-007FH 0040-007FH Mnemonic Location Sbuftx 1FBAH 7DH PWM0CONTROL 1FB0H 7DHSpbaud 1FBCH 7DH Spcon 1FBBH 7DHZeroreg Zeroreg150 Zero This register is always equal to zero Page Glossary Page Glossary DOUBLE-WORD FET ISR PIC PLL PTS SFR Uart Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12