Intel Microcontroller, 80C196NU, 8XC196NP manual 13-16

		CONTENTS
	FIGURES
Figure		Page
13-7	Chip Configuration 1 (CCR1) Register	13-16
13-8	Multiplexing and Bus Width Options	13-19
13-9	Bus Activity for Four Types of Buses	13-20
13-10	16-bit External Devices in Demultiplexed Mode	13-22
13-11	Timings for Multiplexed and Demultiplexed 16-bit Buses (8XC196NP)	13-23
13-12	Timings for Multiplexed and Demultiplexed 8-bit Buses (8XC196NP)	13-25
13-13	READY Timing Diagram — Multi plexed Mode	13-28
13-14	READY Timing Diagram — Demultiplexed Mode (8XC196NP)	13-29
13-15	READY Timing Diagram — Demultiplexed Mode (80C196NU)	13-30
13-16	HOLD#, HLDA# Timing	13-31
13-17	Write-control Signal Waveforms	13-34
13-18	Decoding WRL# and WRH#	13-35
13-19	A System with 8-bit and 16-bit Buses	13-36
13-20	Multiplexed System Bus Timing (8XC196NP)	13-37
13-21	Multiplexed System Bus Timing (80C196NU)	13-38
13-22	Demultiplexed System Bus Timing (8XC196NP)	13-39
13-23	Demultiplexed System Bus Timing (80C196NU)	13-40
13-24	Deferred Bus-cycle Mode Timing Diagram (80C196NU)	13-41
B-1	8XC196NP 100-lead SQFP Package	B-2
B-2	8XC196NP 100-lead QFP Package	B-3
B-3	80C196NU 100-lead SQFP Package	B-4
B-4	80C196NU 100-lead QFP Package	B-5

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