8XC196NP, 80C196NU USER’S MANUAL

Table 6-2. Interrupt and PTS Control and Status Registers (Continued)

Mnemonic

Address

Description

 

 

 

INT_PEND

0009H

Interrupt Pending Registers

INT_PEND1

0012H

The bits in this register are set by hardware to indicate that an

 

 

interrupt is pending.

 

 

 

PSW

No direct access

Processor Status Word

 

 

This register contains one bit that globally enables or disables

 

 

servicing of all maskable interrupts and another that enables or

 

 

disables the PTS. These bits are set or cleared by executing the

 

 

enable interrupts (EI), disable interrupts (DI), enable PTS (EPTS),

 

 

and disable PTS (DPTS) instructions.

 

 

 

PTSSEL

0004H, 0005H

PTS Select Register

 

 

This register selects either a PTS routine or a standard interrupt

 

 

service routine for each of the maskable interrupt requests.

 

 

 

PTSSRV

0006H, 0007H

PTS Service Register

 

 

The bits in this register are set by hardware to request an end-of-

 

 

PTS interrupt.

 

 

 

6.3INTERRUPT SOURCES AND PRIORITIES

Table 6-3 lists the interrupts sources, their default priorities (30 is highest and 0 is lowest), and their vector addresses. The unimplemented opcode and software trap interrupts are not priori- tized; they go directly to the interrupt controller for servicing. The priority encoder determines the priority of all other pending interrupt requests. NMI has the highest priority of all prioritized interrupts, PTS interrupts have the next highest priority, and standard interrupts have the lowest. The priority encoder selects the highest priority pending request and the interrupt controller se- lects the corresponding vector location in special-purpose memory. This vector contains the start- ing (base) address of the corresponding PTS control block (PTSCB) or interrupt service routine. PTSCBs must be located on a quad-word boundary in the internal register file. Interrupt service routines must begin execution in page FFH, but can jump anywhere after the initial vector is tak- en.

6.3.1Special Interrupts

This microcontroller has three special interrupt sources that are always enabled: unimplemented opcode, software trap, and NMI. These interrupts are not affected by the EI (enable interrupts) and DI (disable interrupts) instructions, and they cannot be masked. All of these interrupts are serviced by the interrupt controller; they cannot be assigned to the PTS. Of these three, only NMI goes through the transition detector and priority encoder. The other two special interrupts go di- rectly to the interrupt controller for servicing. Be aware that these interrupts are often assigned to special functions in development tools.

6-4

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Intel 80C196NU, 8XC196NP, Microcontroller Interrupt Sources and Priorities, Special Interrupts, Intpend, Ptssel, Ptssrv
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Microcontroller, 80C196NU, 8XC196NP specifications

The Intel 8XC196NP and 80C196NU microcontrollers are part of Intel's renowned 16-bit microcontroller series that gained popularity in the 1980s and 1990s for embedded systems applications. Designed for a variety of applications, these microcontrollers are characterized by their robust performance, versatility, and industry-standard architecture.

The 8XC196NP features an enhanced instruction set with over 100 instructions, allowing for efficient code execution. It operates at clock speeds up to 16 MHz, which contributes to improved performance in time-sensitive applications. The microcontroller is equipped with a 16-bit data bus, enabling more efficient data handling compared to its 8-bit predecessors, thus accommodating complex algorithms and large data sets.

In terms of memory architecture, the 8XC196NP supports an addressable memory space of up to 64 KB of program memory and 64 KB of data memory. This configuration provides sufficient space for large applications while ensuring fast data access. The microcontroller includes integrated features such as timers, serial I/O capabilities, and interrupt processing, which enhance its functionality for real-time applications and control mechanisms.

The 80C196NU, on the other hand, is designed for lower power operation, making it suitable for battery-powered devices. This microcontroller maintains similar features to the 8XC196NP while offering advancements that support low-power consumption. The 80C196NU can also function in a range of temperature environments, making it adaptable for industrial applications.

Both the 8XC196NP and 80C196NU support external memory interfacing, allowing designers to expand the system's capability by connecting additional ROM and RAM. This flexibility makes them appealing for developing complex systems, such as motor controls, industrial automation, and consumer electronics.

Another standout feature of these microcontrollers is their built-in debugging capabilities. Intel provided hardware and software tools that enabled developers to test and troubleshoot their applications effectively, reducing the development time and increasing reliability.

Overall, the Intel 8XC196NP and 80C196NU microcontrollers stand out for their dependability, versatility, and performance, contributing significantly to the evolution of embedded system design. Their legacy continues to influence modern microcontroller technology, ensuring their relevance in a wide array of applications today.
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