Cypress CYS25G0101DX-ATC

CYS25G0101DX-ATC Evaluation Board User’s Guide

7. Eye Diagram Testing Result

Figure 12 is the Eye Diagram measurement from CYS25G0101DX Evaluation Board by using the test set-up as in Figure 9. In this

measurement, the evaluation board is configured to parallel loop back mode (Figure 7) and with no SONET filter at the oscilloscope.

Figure 12. CYS25G0101DX Evaluation Board Eye Diagram

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Contents

Main Page Page 1. Introduction 2. Features 3. Kit Contents 4. Functional Description Page Page Page Page Page CYS25G0101DX-ATC Evaluation Board Users Guide 11 Figure 3. The Jumper Orientations of the CYS25G0101DX 5. Diagnostic Modes 5.1 Diagnostic Loopback Mode 5.2 Line Loopback Page 5.4 Parallel Line Loopback (TEST0) Mode 5.4.1 Test the Internal RX CDR PLL Only 5.4.2 Test the Internal RX CDR PLL and TX PLL 6. Testing Hookup 6.1 Set-up for BERT Test 6.2 Set-up for Eye Diagram Test 6.3 SONET Jitter Transfer and Jitter Tolerance Test 6.4 Set-up for Testing the TX PLL in Parallel Line Loopback Mode Page Page Page 10. Schematic Diagram, PCB Layout and BOM (Bill of Material)