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NXP Semiconductors LPC2919 DLPC2917/19, Raft Aft, Dra Dr, T Draft, NXP Semiconductors, 12 of

Models: LPC2917 LPC2919

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DRAF

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T DRAFT		T
DRA	DRA DR
F	F
		DRAF
DRAFT DRAFT

										DRAFT DRAFT
	LPC2917/19		ITCM		ARM968E-S	DTCM				DRAFT	D
										DRAFT

			16 Kb			16 Kb

				s						DRA
				s	m
		AHB2DTL	Bridge		m
SYS_CLK	Vectored Interrupt	AHB2DTL	Bridge	s					IEEE 1149.1 JTAG TEST and
SYS_CLK									IEEE 1149.1 JTAG TEST and
									DEBUG INTERFACE
									DEBUG INTERFACE
	Controller (VIC)
	Embedded					s			External Static Memory
	Embedded								Controller (SMC)
	FLASH Memory
	512 - 768 Kb
	FLASH Memory Controller (FMC)			s					Embedded
	FLASH Memory Controller (FMC)								SRAM Memory 16 Kb
						s			SRAM Controller #1
	Modulation and Sampling								SRAM Controller #1
	Modulation and Sampling
	Control Subsystem
MSCSS_CLK									Embedded
MSCSS_CLK	Timer 0, 1 (MTMR)								SRAM Memory 32 Kb
	Timer 0, 1 (MTMR)					s			SRAM Memory 32 Kb
		AHB2VPB	Bridge			s
		AHB2VPB	Bridge	s					SRAM Controller #0
									SRAM Controller #0
	PWM 0, 1, 2, 3
	PWM 0, 1, 2, 3
ADC_CLK	ADC 1, 2
	ADC 1, 2								General Subsystem
							AHB2VPB		Chip Feature ID (CFID)
	CAN Controller					s		Bridge
	CAN Controller							Bridge	System Control Unit (SCU)
									System Control Unit (SCU)
	0, 1								Event Router (ER)
IVNSS_CLK		AHB2VPB	Bridge						General Purpose IO (GPIO)
	2 Kbyte Static RAM	AHB2VPB	Bridge	s					General Purpose IO (GPIO)
	GLOBAL ACCEPTANCE			s					Peripheral Subsystem
	FILTER								Peripheral Subsystem
									0, 1, 2, 3
	LIN MASTER 0/1								Timer (TMR)	TMR_CLK
							2VPBAHB		Timer (TMR)	TMR_CLK
						s		Bridge	0, 1, 2, 3
								Bridge		SPI_CLK

									SPI 0, 1, 2
									SPI 0, 1, 2
									UART 0, 1	UART_CLK
									UART 0, 1
									Watchdog Timer (WDT)	SAFE_CLK
									Watchdog Timer (WDT)
									Power Clock Reset
									Control Subsystem
							AHB2DTL		Clock Generation Unit (CGU)	PCR_CLK
						s		Bridge		PCR_CLK
								Bridge	Reset Generation Unit (RGU)


									Power Management Unit (PMU)

Fig 3. LPC2917/19 block diagram, overview of clock areas

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

12 of 68

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NXP Semiconductors LPC2919 user manual DLPC2917/19, Raft Aft, Dra Dr, T Draft, NXP Semiconductors, Draft Draft, 12 of

Contents

1. Introduction 2. General descriptionLPC2917/19 DLPC2917/19 T DRAFT3. Features DLPC2917/194. Ordering information DLPC2917/195. Block diagram DRA DRDRAFT DRAFT Preliminary data sheet6. Pinning information 6.2.1 General description6.2.2 LQFP144 pin assignment DLPC2917/19Symbol Function 0 defaultDLPC2917/19 RAFT AFTSymbol Function 0 defaultDLPC2917/19 RAFT AFTDLPC2917/19 LQFP144 pinDRAFT 7.1 Reset, debug, test and power description 7.1.1 Reset and power-up behavior7.1.2 Reset strategy 7. Functional description7.1.3 IEEE 1149.1 interface pins JTAG boundary-scan test 7.1.4 Power supply pins description7.2.1 Clock architecture DLPC2917/19DRAF Preliminary data sheetDLPC2917/19 RAFT AFT7.2.2 Base clock and branch clock relationship DLPC2917/19DRAFT DRAFT DRAF Table 7. Base clock and branch clock overview8. Block description 8.1.1 OverviewDLPC2917/19 8.1.2 Description DLPC2917/198.1.3 Flash memory controller pin description 8.1.4 Flash memory controller clock description8.1.5 Flash layout DLPC2917/198.1.6 Flash bridge wait-states DLPC2917/19DRAFT DRAFT Table 9. Flash sector overview …continued8.2.1 Overview 8.2.2 DescriptionDLPC2917/19 8.2.5 External memory timing diagrams 8.2.3 External static-memory controller pin description8.2.4 External static-memory controller clock description Table 12. External memory controller pinsDRAFT DRAFT DRAFT DRAFT DRAFPreliminary data sheet DLPC2917/19DLPC2917/19 RAFT AFTT DRAFT NXP Semiconductors8.3.2 Chip and feature identification 8.3.1 General subsystem clock description8.3.3 System Control Unit SCU 8.3.4 Event router8.4.1 Peripheral subsystem clock description DLPC2917/198.4.3 Timer 8.4.2.4 Watchdog timer clock description8.4.2.1 Overview 8.4.2.2 Description8.4.3.2 Description8.4.3.3 Pin description8.4.3.4 Timer clock description 8.4.4 UARTs8.4.4.1 Overview 8.4.4.2 Description8.4.5 Serial peripheral interface 8.4.4.4 UART clock description8.4.5.1 Overview 8.4.5.2 Functional description8.4.5.3 Modes of operation 8.4.5.4 SPI pin description8.4.5.5 SPI clock description DLPC2917/198.4.6 General-purpose I/O8.4.6.1 Overview8.5.1 Overview8.5.2 Global acceptance filter 8.5.3 CAN pin description8.6.2 LIN pin description 8.7.1 Overview8.7.2 Description DLPC2917/198.7.2.1 Synchronization and trigger features of the MSCSS DLPC2917/19start ADC conditions is valid DLPC2917/19RAFT AFT T DRAFT8.7.3 MSCSS pin description 8.7.4 MSCSS clock descriptionDLPC2917/19 The MSCSS is clocked from a number of different sources8.7.5 Analog-to-digital converter 8.7.5.1 Overview8.7.5.2 Description DLPC2917/198.7.5.3 ADC pin description DLPC2917/19RAFT AFT T DRAFT8.7.6 PWM 8.7.5.4 ADC clock description8.7.6.1 Overview 8.7.6.2 Description8.7.6.3 Synchronizing the PWM counters Fig 10. PWM block diagramDLPC2917/19 8.7.7 Timers in the MSCSS 8.7.6.4 Master and slave mode8.7.6.5 PWM pin description 8.7.6.6 PWM clock description8.7.7.4 MSCSS timer-clock description 8.8.1 Overview8.8.2 Description 8.7.7.2 Description8.8.3 PCR subsystem clock description 8.8.4 Clock Generation Unit CGUPower, Clock & Reset DLPC2917/198.8.4.2 Description DLPC2917/19RAFT AFT T DRAFTDLPC2917/19 RAFT AFTDRA DR T DRAFTDLPC2917/19 DRAFT DRAFT DRAFLPOSC/crystal Oscillator 8.8.4.3 PLL functional description DLPC2917/19RAFT AFT T DRAFT8.8.4.4 CGU pin description Triple output phasesDirect output mode Power-down control8.8.5 Reset Generation Unit RGU 8.8.5.1 Overview8.8.5.2 Description DLPC2917/198.8.6 Power Management Unit PMU 8.8.5.3 RGU pin description8.8.6.1 Overview 8.8.6.2 DescriptionDRAFT DRAFT DRAFTDRAF Implemented Switch On/Off8.9 Vectored interrupt controller 8.9.1 Overview8.9.2 Description DRAFT DRAFT9. Limiting values 8.9.3 VIC pin description8.9.4 VIC clock description DLPC2917/1910. Thermal characteristics DRAFTmADRAFT Symbol11. Static characteristics SymbolDLPC2917/19 RAFT AFTDRAFTUnit DRAFTTable 30. Static characteristics …continued Symbol12. Dynamic characteristics Table 30. Static characteristics …continuedSymbol SymbolUnitDRAFT DLPC2917/19DRAFT DRAFT DRAFTTable 31. Dynamic characteristics …continued SymbolJitter Specification DLPC2917/1913. Package outline Preliminary data sheetDLPC2917/19 RAFT AFT14. Soldering 14.1 Introduction14.2 Through-hole mount packages 14.3 Surface mount packages14.3.2 Wave soldering DLPC2917/19DRAFT DRAFT MSL Moisture Sensitivity Level14.3.3 Manual soldering DLPC2917/19DLPC2917/19 Package1Soldering method Dipping15. Abbreviations DLPC2917/19RAFT AFT DRA DR16. References DLPC2917/19RAFT AFT DRA DR17. Revision history DLPC2917/19DRAFT DRAFT DRAF Table 36. Revision history18. Legal information 19. Contact informationDLPC2917/19 For sales office addresses, send an email to salesaddresses@nxp.com20. Contents continuedDLPC2917/19 T DRAFT 9 Limiting values 10 Thermal characteristics11 Static characteristics 12 Dynamic characteristics 19 Contact information 20 Contents