LPC2917/19 | NXP Semiconductors LPC2919 specification

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T DRAFT		T
DRA	DRA DR
F	F
		DRAF
DRAFT DRAFT

										DRAFT DRAFT
	LPC2917/19		ITCM		ARM968E-S	DTCM				DRAFT	D
										DRAFT

			16 Kb			16 Kb

				s						DRA
				s	m
		AHB2DTL	Bridge		m
SYS_CLK	Vectored Interrupt	AHB2DTL	Bridge	s					IEEE 1149.1 JTAG TEST and
SYS_CLK									IEEE 1149.1 JTAG TEST and
									DEBUG INTERFACE
									DEBUG INTERFACE
	Controller (VIC)
	Embedded					s			External Static Memory
	Embedded								Controller (SMC)
	FLASH Memory
	512 - 768 Kb
	FLASH Memory Controller (FMC)			s					Embedded
	FLASH Memory Controller (FMC)								SRAM Memory 16 Kb
						s			SRAM Controller #1
	Modulation and Sampling								SRAM Controller #1
	Modulation and Sampling
	Control Subsystem
MSCSS_CLK									Embedded
MSCSS_CLK	Timer 0, 1 (MTMR)								SRAM Memory 32 Kb
	Timer 0, 1 (MTMR)					s			SRAM Memory 32 Kb
		AHB2VPB	Bridge			s
		AHB2VPB	Bridge	s					SRAM Controller #0
									SRAM Controller #0
	PWM 0, 1, 2, 3
	PWM 0, 1, 2, 3
ADC_CLK	ADC 1, 2
	ADC 1, 2								General Subsystem
							AHB2VPB		Chip Feature ID (CFID)
	CAN Controller					s		Bridge
	CAN Controller							Bridge	System Control Unit (SCU)
									System Control Unit (SCU)
	0, 1								Event Router (ER)
IVNSS_CLK		AHB2VPB	Bridge						General Purpose IO (GPIO)
	2 Kbyte Static RAM	AHB2VPB	Bridge	s					General Purpose IO (GPIO)
	GLOBAL ACCEPTANCE			s					Peripheral Subsystem
	FILTER								Peripheral Subsystem
									0, 1, 2, 3
	LIN MASTER 0/1								Timer (TMR)	TMR_CLK
							2VPBAHB		Timer (TMR)	TMR_CLK
						s		Bridge	0, 1, 2, 3
								Bridge		SPI_CLK

									SPI 0, 1, 2
									SPI 0, 1, 2
									UART 0, 1	UART_CLK
									UART 0, 1
									Watchdog Timer (WDT)	SAFE_CLK
									Watchdog Timer (WDT)
									Power Clock Reset
									Control Subsystem
							AHB2DTL		Clock Generation Unit (CGU)	PCR_CLK
						s		Bridge		PCR_CLK
								Bridge	Reset Generation Unit (RGU)


									Power Management Unit (PMU)

Fig 3. LPC2917/19 block diagram, overview of clock areas

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

12 of 68

Image 12

NXP Semiconductors LPC2919 user manual LPC2917/19 block diagram, overview of clock areas

Contents

Introduction General descriptionAbout this document Intended audience NXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Ordering information Ordering optionsOrdering information Part options Block diagram LPC2917/19 block diagram Pinning information PinningPin description General description Symbol Pin Description Function 0 default LQFP144 pin assignment … TIMER2 MAT2 PWM TRAP1 TIMER2 MAT3 PWM TRAP0TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1 Symbol Pin DescriptionLQFP144 pin Reset, debug, test and power description Reset and power-up behaviorReset strategy Reset pin Ieee 1149.1 interface pins Jtag boundary-scan test Power supply pins descriptionClocking strategy Clock architecture LPC2917/19 block diagram, overview of clock areas LPC2917/19 Base clock and branch clock relationship Base clock and branch clock overviewBase clock Branch clock name Parts of the device clocked by This branch clock Block description Flash memory controllerOverview Base clock DRA Description Flash memory controller pin description Flash memory controller clock descriptionFlash layout Flash bridge wait-states Flash sector overview … 32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External memory timing diagrams External memory controller pinsExternal static-memory controller pin description External static-memory controller clock description Reading from external memory Writing to external memory Reading/writing external memory Chip and feature identification General subsystemGeneral subsystem clock description System Control Unit SCU Symbol Direction Bit position Description Default Polarity Peripheral subsystemPeripheral subsystem clock description Event-router pin connections Timer Watchdog timer clock descriptionPin description 3.2 Description 3.3 Pin description Timer clock description Timer pinsUart pins UARTs Serial peripheral interface Uart clock descriptionFunctional description SPI pins Modes of operationSPI pin description SPI clock description Gpio pins General-purpose I/O6.1 Overview Gpio pin description Can pins Can gatewayLIN Global acceptance filter LIN controller pins Modulation and sampling control subsystemLIN pin description LIN0/1 Txdl Synchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagram Start ADC conditions is valid Mscss pin description Mscss clock description Draft Analog-to-digital converter ADC block diagram Analog to digital converter pinsADC pin description 6 PWM ADC clock description PWM block diagram Synchronizing the PWM counters Timers in the Mscss Master and slave modePWM pins PWM pin description Power, clock and reset control subsystem Mscss timer-clock descriptionMscss timer 1 pin Pause pin for Mscss timer Pcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU CGU base clocks Number Name Frequency Description MHz Block diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset Generation Unit RGU Reset output configuration Power Management Unit PMU RGU pinsRGU pin description DRA Vectored interrupt controller PMU pin description Limiting values VIC pin descriptionVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as input Analog-to-digital converter supply VDDA5V FSRINL LSB Dynamic characteristics Power-up resetDynamic characteristics Symbol Parameter Conditions Min Typ Max Unit UnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Package outline Package outline SOT486-1 LQFP144 Soldering IntroductionThrough-hole mount packages Surface mount packages Volume mm3 350 235 220 Lead-free process from J-STD-020C Temperature profiles for large and small componentsWave soldering SnPb eutectic process from J-STD-020C Package thickness mm Package related soldering information Mounting Package1 Soldering method Wave Reflow2 DippingCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SIL Mounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Legal information Contact information Contents Contact information Contents SolderingPackage outline