Reading/writing external memory | NXP Semiconductors LPC2917

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T DRAFT		T
DRA		DRA	DR
F		F
are added between a read and a write cycle in the same external memory DRAFTdevice.	DRAFT		DRAF
Usage of the idle/turn-around time (IDCY) is demonstrated In Figure 6. Extra wait states

		DRAFT DRAFT
		DRAFT	D
CLK(SYS)		DRAFT
CLK(SYS)		DRA
		DRA
CS
WE_N / BLS
OE_N
ADDR
DATA
WSTOEN		WSTWEN
WST1	IDCY	WST2
WSTOEN=5, WSTWEN=5, WST1=7, WST2=6, IDCY=5
Fig 6. Reading/writing external memory

Address pins on the device are shared with other functions. When connecting external memories, check that the I/O pin is programmed for the correct function. Control of these settings is handled by the SCU.

LPC2917_19_1

Preliminary data sheet

Rev. 1.01 — 15 November 2007

21 of 68

Page 21

Image 21

NXP Semiconductors LPC2917, LPC2919 user manual Reading/writing external memory

Contents

General description IntroductionAbout this document Intended audience NXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Ordering options Ordering informationOrdering information Part options LPC2917/19 block diagram Block diagram Pinning Pinning informationPin description General description LQFP144 pin assignment … Symbol Pin Description Function 0 default TIMER2 MAT3 PWM TRAP0 TIMER2 MAT2 PWM TRAP1TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1 Symbol Pin DescriptionLQFP144 pin Reset and power-up behavior Reset, debug, test and power descriptionReset strategy Reset pin Power supply pins description Ieee 1149.1 interface pins Jtag boundary-scan testClocking strategy Clock architecture LPC2917/19 LPC2917/19 block diagram, overview of clock areas Base clock and branch clock overview Base clock and branch clock relationshipBase clock Branch clock name Parts of the device clocked by This branch clock Flash memory controller Block descriptionOverview Base clock Description DRA Flash memory controller pin description Flash memory controller clock descriptionFlash layout Flash sector overview … Flash bridge wait-states 32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External memory controller pins External memory timing diagramsExternal static-memory controller pin description External static-memory controller clock description Writing to external memory Reading from external memory Reading/writing external memory General subsystem Chip and feature identificationGeneral subsystem clock description System Control Unit SCU Peripheral subsystem Symbol Direction Bit position Description Default PolarityPeripheral subsystem clock description Event-router pin connections Timer Watchdog timer clock descriptionPin description 3.3 Pin description 3.2 Description Timer pins Timer clock descriptionUart pins UARTs Serial peripheral interface Uart clock descriptionFunctional description Modes of operation SPI pinsSPI pin description SPI clock description General-purpose I/O Gpio pins6.1 Overview Gpio pin description Can gateway Can pinsLIN Global acceptance filter Modulation and sampling control subsystem LIN controller pinsLIN pin description LIN0/1 Txdl Modulation and sampling control subsystem block diagram Synchronization and trigger features of the Mscss Start ADC conditions is valid Mscss clock description Mscss pin description Analog-to-digital converter Draft ADC block diagram Analog to digital converter pinsADC pin description ADC clock description 6 PWM Synchronizing the PWM counters PWM block diagram Master and slave mode Timers in the MscssPWM pins PWM pin description Mscss timer-clock description Power, clock and reset control subsystemMscss timer 1 pin Pause pin for Mscss timer Pcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocks Block diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset output configuration Reset Generation Unit RGU Power Management Unit PMU RGU pinsRGU pin description DRA PMU pin description Vectored interrupt controller Limiting values VIC pin descriptionVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as input VDDA5V FSR Analog-to-digital converter supplyINL LSB Power-up reset Dynamic characteristicsDynamic characteristics Symbol Parameter Conditions Min Typ Max Unit UnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter Specification Package outline SOT486-1 LQFP144 Package outline Introduction SolderingThrough-hole mount packages Surface mount packages Temperature profiles for large and small components Volume mm3 350 235 220 Lead-free process from J-STD-020CWave soldering SnPb eutectic process from J-STD-020C Package thickness mm Mounting Package1 Soldering method Wave Reflow2 Dipping Package related soldering informationCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SIL Mounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Contact information Legal information Contents Contact information Contents SolderingPackage outline

NXP Semiconductors

DLPC2917/19

T DRAFT

DRA

Fig 6. Reading/writing external memory