NXP Semiconductors
DRAFT | D | D |
| AFT |
RAFT | RAFT AFT | |||
|
|
| DR | DR |
DLPC2917/19
ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT
Table 7.
Base clock
BASE_MSCSS_CLK
Branch clock name
CLK_MSCSS_VPB
CLK_MSCSS_MTMR0
CLK_MSCSS_MTMR1
CLK_MSCSS_PWM0
CLK_MSCSS_PWM1
CLK_MSCSS_PWM2
CLK_MSCSS_PWM3
CLK_MSCSS_ADC1_V PB
T | DRAFT |
| T |
| |
DRA |
| DRA |
| DR | |
F |
|
| F |
|
|
| DRAFT DRAF | ||||
Parts of the device clockedDRAFTby Remark | DRAFT | ||||
VPB side of the MSCSS | DRAFT | ||||
this branch clock |
|
|
|
|
|
Timer 0 in the MSCSS |
| DRAFT | D | ||
|
| ||||
|
|
|
|
| |
Timer 1 in the MSCSS |
|
|
| DRA | |
PWM 0 |
|
|
| ||
|
|
|
|
|
PWM 0
PWM 0
PWM 0
VPB side of ADC 1
BASE_UART_CLK
BASE_SPI_CLK
BASE_TMR_CLK
BASE_ADC_CLK
BASE_CLK_TESTSHELL
CLK_MSCSS_ADC2_V VPB side of ADC 2
PB
CLK_UART0 | UART 0 interface clock |
CLK_UART1 | UART 1 interface clock |
CLK_SPI0 | SPI 0 interface clock |
|
|
CLK_SPI1 | SPI 1 interface clock |
|
|
CLK_SPI2 | SPI 2 interface clock |
CLK_TMR0 | Timer 0 clock for counter part |
|
|
CLK_TMR1 | Timer 1 clock for counter part |
|
|
CLK_TMR2 | Timer 2 clock for counter part |
|
|
CLK_TMR3 | Timer 3 clock for counter part |
CLK_ADC1 | Control of ADC 1, capture sample |
| result |
|
|
CLK_ADC2 | Control of ADC 2, capture sample |
| result |
CLK_TESTSHELL_IP |
|
[1]This clock is always on (cannot be switched off for system safety reasons)
[2]In the peripheral subsystem parts of the Timers, Watchdog Timer, SPI and UART have their own clock source. See Section 8.4 for details.
[3]In the Power Clock and Reset Control subsystem parts of the CGU, RGU PMU have their own clock source. See Section 8.8 for details.
[4]The clock should remain activated when system
8.Block description
8.1Flash memory controller
8.1.1Overview
The Flash Memory Controller (FMC) interfaces to the embedded flash memory for two tasks:
•Providing memory data transfer
•Memory configuration via triggering, programming and erasing
LPC2917_19_1 | © NXP B.V. 2007. All rights reserved. |
Preliminary data sheet | Rev. 1.01 — 15 November 2007 | 14 of 68 |