NXP Semiconductors LPC2917 Serial peripheral interface, UART clock description, Overview, T Draft

NXP Semiconductors

DRAFT	D	D		AFT
	RAFT	RAFT AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

	DRA	DRA		DR
	F	F
8.4.4.4 UART clock description	T DRAFT	T
	DRAFT DRAFT DRAF
The UART modules are clocked by two different clocks; CLK_SYS_PESS and
CLK_UARTx (x = 0-1), see Section 7.2.2. Note that each UART has its own CLK UARTx
	DRAFT DRAFT
branch clock for power management. The frequency of all CLK_UARTx clocks is identical				D
since they are derived from the same base clock BASE_CLK_UART. The register		DRAFT
interface towards the system bus is clocked by CLK_SYS_PESS. The baud generator is			DRA
clocked by the CLK_UARTx.

8.4.5 Serial peripheral interface

8.4.5.1Overview

The LPC2917/19 contains three Serial Peripheral Interface modules (SPIs) to allow synchronous serial communication with slave or master peripherals.

The key features are:

•Master or slave operation

•Supports up to four slaves in sequential multi-slave operation

•Supports timer-triggered operation

•Programmable clock bit rate and prescale based on SPI source clock (BASE_SPI_CLK), independent of system clock

•Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep

•Programmable choice of interface operation: Motorola SPI or Texas Instruments Synchronous Serial Interfaces

•Programmable data-frame size from 4 to 16 bits

•Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts

•Serial clock-rate master mode: fserial_clk ≤ fCLK(SPI)*/2

•Serial clock-rate slave mode: fserial_clk = fCLK(SPI)*/4

•Internal loopback test mode

8.4.5.2Functional description

The SPI module is a master or slave interface for synchronous serial communication with peripheral devices that have either Motorola SPI or Texas Instruments Synchronous Serial Interfaces.

The SPI module performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with FIFO memories (16 bits wide x 32 words deep). Serial data is transmitted on SPI_TxD and received on SPI_RxD.

The SPI module includes a programmable bit-rate clock divider and prescaler to generate the SPI serial clock from the input clock CLK_SPIx.

The SPI module’s operating mode, frame format, and word size are programmed through the SLVn_SETTINGS registers.

A single combined interrupt request SPI_INTREQ output is asserted if any of the interrupts are asserted and unmasked.

LPC2917_19_1 © NXP B.V. 2007. All rights reserved.

Preliminary data sheet Rev. 1.01 — 15 November 2007 27 of 68