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NXP Semiconductors LPC2919 user manual Revision history, DLPC2917/19, Draft Draft Draf

Models: LPC2917 LPC2919

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NXP Semiconductors

17. Revision history

Table 36. Revision history


Document ID	Release date		Data sheet status
LPC2917_19_1.01	<tbd>		Preliminary data sheet
Modifications	•	Part LPC2915 removed
	•	Editorial updates
LPC2915_17_19_1	20070917		Preliminary data sheet

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19
ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT
T DRAFT		T
DRA		DRA DR
F		F
DRAFT DRAFT DRAF
Change notice Supersedes	DRAFT DRAFT
		DRAFT	D
LPC2915_17_19_1

		DRA

LPC2917_19_1

Preliminary data sheet

Rev. 1.01 — 15 November 2007

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NXP Semiconductors LPC2919 user manual Revision history, DLPC2917/19, Draft Draft Draf

Contents

LPC2917/19 1. Introduction2. General description T DRAFT DLPC2917/19DLPC2917/19 3. FeaturesDLPC2917/19 4. Ordering informationDRA DR 5. Block diagramDRAFT DRAFT Preliminary data sheet6.2.1 General description 6. Pinning information6.2.2 LQFP144 pin assignment DLPC2917/19Function 0 default SymbolDLPC2917/19 RAFT AFTFunction 0 default SymbolDLPC2917/19 RAFT AFTDRAFT DLPC2917/19LQFP144 pin 7.1.1 Reset and power-up behavior 7.1 Reset, debug, test and power description7.1.2 Reset strategy 7. Functional description7.1.4 Power supply pins description 7.1.3 IEEE 1149.1 interface pins JTAG boundary-scan test7.2.1 Clock architecture DLPC2917/19Preliminary data sheet DRAFDLPC2917/19 RAFT AFTDLPC2917/19 7.2.2 Base clock and branch clock relationshipDRAFT DRAFT DRAF Table 7. Base clock and branch clock overviewDLPC2917/19 8. Block description8.1.1 Overview DLPC2917/19 8.1.2 Description8.1.4 Flash memory controller clock description 8.1.3 Flash memory controller pin description8.1.5 Flash layout DLPC2917/19DLPC2917/19 8.1.6 Flash bridge wait-statesDRAFT DRAFT Table 9. Flash sector overview …continuedDLPC2917/19 8.2.1 Overview8.2.2 Description 8.2.3 External static-memory controller pin description 8.2.5 External memory timing diagrams8.2.4 External static-memory controller clock description Table 12. External memory controller pinsDRAFT DRAFT DRAF DRAFT DRAFTPreliminary data sheet DLPC2917/19RAFT AFT DLPC2917/19T DRAFT NXP Semiconductors8.3.1 General subsystem clock description 8.3.2 Chip and feature identification8.3.3 System Control Unit SCU 8.3.4 Event routerDLPC2917/19 8.4.1 Peripheral subsystem clock description8.4.2.4 Watchdog timer clock description 8.4.3 Timer8.4.2.1 Overview 8.4.2.2 DescriptionDescription 8.4.3.28.4.3.3 Pin description8.4.4 UARTs 8.4.3.4 Timer clock description8.4.4.1 Overview 8.4.4.2 Description8.4.4.4 UART clock description 8.4.5 Serial peripheral interface8.4.5.1 Overview 8.4.5.2 Functional description8.4.5.4 SPI pin description 8.4.5.3 Modes of operation8.4.5.5 SPI clock description DLPC2917/19General-purpose I/O 8.4.68.4.6.1 OverviewOverview 8.5.18.5.2 Global acceptance filter 8.5.3 CAN pin description8.7.1 Overview 8.6.2 LIN pin description8.7.2 Description DLPC2917/19DLPC2917/19 8.7.2.1 Synchronization and trigger features of the MSCSSDLPC2917/19 start ADC conditions is validRAFT AFT T DRAFT8.7.4 MSCSS clock description 8.7.3 MSCSS pin descriptionDLPC2917/19 The MSCSS is clocked from a number of different sources8.7.5.1 Overview 8.7.5 Analog-to-digital converter8.7.5.2 Description DLPC2917/19DLPC2917/19 8.7.5.3 ADC pin descriptionRAFT AFT T DRAFT8.7.5.4 ADC clock description 8.7.6 PWM8.7.6.1 Overview 8.7.6.2 DescriptionDLPC2917/19 8.7.6.3 Synchronizing the PWM countersFig 10. PWM block diagram 8.7.6.4 Master and slave mode 8.7.7 Timers in the MSCSS8.7.6.5 PWM pin description 8.7.6.6 PWM clock description8.8.1 Overview 8.7.7.4 MSCSS timer-clock description8.8.2 Description 8.7.7.2 Description8.8.4 Clock Generation Unit CGU 8.8.3 PCR subsystem clock descriptionPower, Clock & Reset DLPC2917/19DLPC2917/19 8.8.4.2 DescriptionRAFT AFT T DRAFTRAFT AFT DLPC2917/19DRA DR T DRAFTLPOSC/crystal Oscillator DLPC2917/19DRAFT DRAFT DRAF DLPC2917/19 8.8.4.3 PLL functional descriptionRAFT AFT T DRAFTTriple output phases 8.8.4.4 CGU pin descriptionDirect output mode Power-down control8.8.5.1 Overview 8.8.5 Reset Generation Unit RGU8.8.5.2 Description DLPC2917/198.8.5.3 RGU pin description 8.8.6 Power Management Unit PMU8.8.6.1 Overview 8.8.6.2 DescriptionDRAFT DRAFT DRAFTDRAF Implemented Switch On/Off8.9.1 Overview 8.9 Vectored interrupt controller8.9.2 Description DRAFT DRAFT8.9.3 VIC pin description 9. Limiting values8.9.4 VIC clock description DLPC2917/19DRAFTmA 10. Thermal characteristicsDRAFT SymbolSymbol 11. Static characteristicsDLPC2917/19 RAFT AFTDRAFT DRAFTUnitTable 30. Static characteristics …continued SymbolTable 30. Static characteristics …continued 12. Dynamic characteristicsSymbol SymbolDLPC2917/19 UnitDRAFTDRAFT DRAFT DRAFTSymbol Table 31. Dynamic characteristics …continuedJitter Specification DLPC2917/19Preliminary data sheet 13. Package outlineDLPC2917/19 RAFT AFT14.1 Introduction 14. Soldering14.2 Through-hole mount packages 14.3 Surface mount packagesDLPC2917/19 14.3.2 Wave solderingDRAFT DRAFT MSL Moisture Sensitivity LevelDLPC2917/19 14.3.3 Manual solderingPackage1 DLPC2917/19Soldering method DippingDLPC2917/19 15. AbbreviationsRAFT AFT DRA DRDLPC2917/19 16. ReferencesRAFT AFT DRA DRDLPC2917/19 17. Revision historyDRAFT DRAFT DRAF Table 36. Revision history19. Contact information 18. Legal informationDLPC2917/19 For sales office addresses, send an email to salesaddresses@nxp.comDLPC2917/19 20. Contentscontinued 9 Limiting values 10 Thermal characteristics T DRAFT11 Static characteristics 12 Dynamic characteristics 19 Contact information 20 Contents