Reading from external memory

NXP Semiconductors

Fig 4.

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT

withDRAFTCANDRAFTand LINDRAFT

T DRAFT

DRA

DRA DR

DRAFT DRAFT DRAF

CLK(SYS)

DRAFT DRAFT

DRAFT

DRA

OE_N

ADDR

DATA

WSTOEN

WST1

WSTOEN=3, WST1=7

A timing diagram for writing to external memory is shown In Figure 5. The relationship between wait-state settings is indicated with arrows.

CLK(SYS)

WE_N / BLS

ADDR

DATA

WSTWEN

WST2

WSTWEN=3, WST2=7

Fig 5. Writing to external memory

LPC2917_19_1

Preliminary data sheet

Rev. 1.01 — 15 November 2007

20 of 68

Page 20

Image 20

NXP Semiconductors LPC2919, LPC2917 user manual Reading from external memory, Writing to external memory

Contents

Introduction General descriptionAbout this document Intended audience On-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Ordering information Ordering optionsOrdering information Part options Block diagram LPC2917/19 block diagram Pinning information PinningPin description General description Symbol Pin Description Function 0 default LQFP144 pin assignment … TIMER2 MAT2 PWM TRAP1 TIMER2 MAT3 PWM TRAP0TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1 LQFP144 pin SymbolPin Description Reset, debug, test and power description Reset and power-up behaviorReset strategy Reset pin Ieee 1149.1 interface pins Jtag boundary-scan test Power supply pins descriptionClocking strategy Clock architecture LPC2917/19 block diagram, overview of clock areas LPC2917/19 Base clock and branch clock relationship Base clock and branch clock overviewBase clock Branch clock name Parts of the device clocked by This branch clock Block description Flash memory controllerOverview Base clock DRA Description Flash layout Flash memory controller pin descriptionFlash memory controller clock description Flash bridge wait-states Flash sector overview … External memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External memory timing diagrams External memory controller pinsExternal static-memory controller pin description External static-memory controller clock description Reading from external memory Writing to external memory Reading/writing external memory Chip and feature identification General subsystemGeneral subsystem clock description System Control Unit SCU Symbol Direction Bit position Description Default Polarity Peripheral subsystemPeripheral subsystem clock description Event-router pin connections Pin description TimerWatchdog timer clock description 3.2 Description 3.3 Pin description Timer clock description Timer pinsUart pins UARTs Functional description Serial peripheral interfaceUart clock description SPI pins Modes of operationSPI pin description SPI clock description Gpio pins General-purpose I/O6.1 Overview Gpio pin description Can pins Can gatewayLIN Global acceptance filter LIN controller pins Modulation and sampling control subsystemLIN pin description LIN0/1 Txdl Synchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagram Start ADC conditions is valid Mscss pin description Mscss clock description Draft Analog-to-digital converter ADC pin description ADC block diagramAnalog to digital converter pins 6 PWM ADC clock description PWM block diagram Synchronizing the PWM counters Timers in the Mscss Master and slave modePWM pins PWM pin description Power, clock and reset control subsystem Mscss timer-clock descriptionMscss timer 1 pin Pause pin for Mscss timer Clock Generation Unit CGU Pcrss block diagramPCR subsystem clock description CGU base clocks Number Name Frequency Description MHz Block diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset Generation Unit RGU Reset output configuration RGU pin description Power Management Unit PMURGU pins DRA Vectored interrupt controller PMU pin description VIC clock description Limiting valuesVIC pin description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as input Analog-to-digital converter supply VDDA5V FSRINL LSB Dynamic characteristics Power-up resetDynamic characteristics Symbol Parameter Conditions Min Typ Max Unit UnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Package outline Package outline SOT486-1 LQFP144 Soldering IntroductionThrough-hole mount packages Surface mount packages Volume mm3 350 235 220 Lead-free process from J-STD-020C Temperature profiles for large and small componentsWave soldering SnPb eutectic process from J-STD-020C Package thickness mm Package related soldering information Mounting Package1 Soldering method Wave Reflow2 DippingCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SIL Mounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact information Contents Package outline Contact information ContentsSoldering

NXP Semiconductors LPC2919, LPC2917 Reading from external memory, Writing to external memory

Models: LPC2917 LPC2919