Manuals / NXP Semiconductors / Computer Equipment / Network Router

NXP Semiconductors LPC2919 Draft Draft Draf, DLPC2917/19, Raft Aft, Dra Dr, T Draft, Clksys

Models: LPC2917 LPC2919

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NXP Semiconductors

Fig 4.

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT

withDRAFTCANDRAFTand LINDRAFT

T DRAFT

DRA

DRA DR

DRAFT DRAFT DRAF

CLK(SYS)

DRAFT DRAFT

DRAFT

DRA

OE_N

ADDR

DATA

WSTOEN

WST1

WSTOEN=3, WST1=7

Reading from external memory

A timing diagram for writing to external memory is shown In Figure 5. The relationship between wait-state settings is indicated with arrows.

CLK(SYS)

WE_N / BLS

ADDR

DATA

WSTWEN

WST2

WSTWEN=3, WST2=7

Fig 5. Writing to external memory

LPC2917_19_1

Preliminary data sheet

Rev. 1.01 — 15 November 2007

20 of 68

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NXP Semiconductors LPC2919 Draft Draft Draf, DLPC2917/19, Raft Aft, Dra Dr, T Draft, NXP Semiconductors, Clksys, 20 of

Contents

LPC2917/19 1. Introduction2. General description DLPC2917/19 T DRAFT3. Features DLPC2917/194. Ordering information DLPC2917/195. Block diagram DRA DRDRAFT DRAFT Preliminary data sheet6. Pinning information 6.2.1 General description6.2.2 LQFP144 pin assignment DLPC2917/19Symbol Function 0 defaultDLPC2917/19 RAFT AFTSymbol Function 0 defaultDLPC2917/19 RAFT AFTDRAFT DLPC2917/19LQFP144 pin 7.1 Reset, debug, test and power description 7.1.1 Reset and power-up behavior7.1.2 Reset strategy 7. Functional description7.1.3 IEEE 1149.1 interface pins JTAG boundary-scan test 7.1.4 Power supply pins description7.2.1 Clock architecture DLPC2917/19DRAF Preliminary data sheetDLPC2917/19 RAFT AFT7.2.2 Base clock and branch clock relationship DLPC2917/19DRAFT DRAFT DRAF Table 7. Base clock and branch clock overviewDLPC2917/19 8. Block description8.1.1 Overview 8.1.2 Description DLPC2917/198.1.3 Flash memory controller pin description 8.1.4 Flash memory controller clock description8.1.5 Flash layout DLPC2917/198.1.6 Flash bridge wait-states DLPC2917/19DRAFT DRAFT Table 9. Flash sector overview …continuedDLPC2917/19 8.2.1 Overview8.2.2 Description 8.2.5 External memory timing diagrams 8.2.3 External static-memory controller pin description8.2.4 External static-memory controller clock description Table 12. External memory controller pinsDRAFT DRAFT DRAFT DRAFT DRAFPreliminary data sheet DLPC2917/19DLPC2917/19 RAFT AFTT DRAFT NXP Semiconductors8.3.2 Chip and feature identification 8.3.1 General subsystem clock description8.3.3 System Control Unit SCU 8.3.4 Event router8.4.1 Peripheral subsystem clock description DLPC2917/198.4.3 Timer 8.4.2.4 Watchdog timer clock description8.4.2.1 Overview 8.4.2.2 Description8.4.3.2 Description8.4.3.3 Pin description8.4.3.4 Timer clock description 8.4.4 UARTs8.4.4.1 Overview 8.4.4.2 Description8.4.5 Serial peripheral interface 8.4.4.4 UART clock description8.4.5.1 Overview 8.4.5.2 Functional description8.4.5.3 Modes of operation 8.4.5.4 SPI pin description8.4.5.5 SPI clock description DLPC2917/198.4.6 General-purpose I/O8.4.6.1 Overview8.5.1 Overview8.5.2 Global acceptance filter 8.5.3 CAN pin description8.6.2 LIN pin description 8.7.1 Overview8.7.2 Description DLPC2917/198.7.2.1 Synchronization and trigger features of the MSCSS DLPC2917/19start ADC conditions is valid DLPC2917/19RAFT AFT T DRAFT8.7.3 MSCSS pin description 8.7.4 MSCSS clock descriptionDLPC2917/19 The MSCSS is clocked from a number of different sources8.7.5 Analog-to-digital converter 8.7.5.1 Overview8.7.5.2 Description DLPC2917/198.7.5.3 ADC pin description DLPC2917/19RAFT AFT T DRAFT8.7.6 PWM 8.7.5.4 ADC clock description8.7.6.1 Overview 8.7.6.2 DescriptionDLPC2917/19 8.7.6.3 Synchronizing the PWM countersFig 10. PWM block diagram 8.7.7 Timers in the MSCSS 8.7.6.4 Master and slave mode8.7.6.5 PWM pin description 8.7.6.6 PWM clock description8.7.7.4 MSCSS timer-clock description 8.8.1 Overview8.8.2 Description 8.7.7.2 Description8.8.3 PCR subsystem clock description 8.8.4 Clock Generation Unit CGUPower, Clock & Reset DLPC2917/198.8.4.2 Description DLPC2917/19RAFT AFT T DRAFTDLPC2917/19 RAFT AFTDRA DR T DRAFTLPOSC/crystal Oscillator DLPC2917/19DRAFT DRAFT DRAF 8.8.4.3 PLL functional description DLPC2917/19RAFT AFT T DRAFT8.8.4.4 CGU pin description Triple output phasesDirect output mode Power-down control8.8.5 Reset Generation Unit RGU 8.8.5.1 Overview8.8.5.2 Description DLPC2917/198.8.6 Power Management Unit PMU 8.8.5.3 RGU pin description8.8.6.1 Overview 8.8.6.2 DescriptionDRAFT DRAFT DRAFTDRAF Implemented Switch On/Off8.9 Vectored interrupt controller 8.9.1 Overview8.9.2 Description DRAFT DRAFT9. Limiting values 8.9.3 VIC pin description8.9.4 VIC clock description DLPC2917/1910. Thermal characteristics DRAFTmADRAFT Symbol11. Static characteristics SymbolDLPC2917/19 RAFT AFTDRAFTUnit DRAFTTable 30. Static characteristics …continued Symbol12. Dynamic characteristics Table 30. Static characteristics …continuedSymbol SymbolUnitDRAFT DLPC2917/19DRAFT DRAFT DRAFTTable 31. Dynamic characteristics …continued SymbolJitter Specification DLPC2917/1913. Package outline Preliminary data sheetDLPC2917/19 RAFT AFT14. Soldering 14.1 Introduction14.2 Through-hole mount packages 14.3 Surface mount packages14.3.2 Wave soldering DLPC2917/19DRAFT DRAFT MSL Moisture Sensitivity Level14.3.3 Manual soldering DLPC2917/19DLPC2917/19 Package1Soldering method Dipping15. Abbreviations DLPC2917/19RAFT AFT DRA DR16. References DLPC2917/19RAFT AFT DRA DR17. Revision history DLPC2917/19DRAFT DRAFT DRAF Table 36. Revision history18. Legal information 19. Contact informationDLPC2917/19 For sales office addresses, send an email to salesaddresses@nxp.comDLPC2917/19 20. Contentscontinued T DRAFT 9 Limiting values 10 Thermal characteristics11 Static characteristics 12 Dynamic characteristics 19 Contact information 20 Contents