NXP Semiconductors
DRAFT | D | D |
| AFT |
RAFT | RAFT AFT | |||
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| DR | DR |
DLPC2917/19
ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT
T | DRAFT | T |
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DRA |
| DRA |
| DR |
F |
| F |
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cannot be performed at full speed (i.e. with zero | DRAF | |||
Remark: If the programmed number of |
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reading is active. | DRAFT DRAFT | |||
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8.2 External static memory controller |
| DRAFT | D | |
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8.2.1Overview
The LPC2917/19 contains an external Static Memory Controller (SMC) which provides an interface for external
Key features are:
DRA
•Supports static
•Asynchronous
•Asynchronous
•Independent configuration for up to eight banks, each up to 16 MB
•Programmable
•Programmable read and write wait states (up to 32), for static RAM devices
•Programmable initial and subsequent
•Programmable write protection
•Programmable
•Programmable external data width:
•Programmable
8.2.2Description
The SMC simultaneously supports up to eight independently configurable memory banks. Each memory bank can be 8, 16 or 32 bits wide and is capable of supporting SRAM, ROM,
A separate
Table 10. External
| 32 bit | Symbol | Description |
| System |
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| Address Bit |
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| field |
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| 31 to 29 | BA[2:0] | external |
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| the base address can be found in the memory map; see Ref. 1. This |
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| field contains ’010’ when addressing an external memory bank. |
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| 28 to 26 | CS[2:0] | |
| 25 and 24 | - | always ’00’; other values are ’mirrors’ of the 16 MByte bank address |
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| 23 to 0 | A[23:0] | |
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LPC2917_19_1 |
| © NXP B.V. 2007. All rights reserved. |
Preliminary data sheet | Rev. 1.01 — 15 November 2007 | 18 of 68 |