NXP Semiconductors
DRAFT | D | D |
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DLPC2917/19
ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT
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or following a PWM). The capture inputs of both timers can also be used toDRAFTcaptureDRAFTthe | DRAF | |||||
control. Several other trigger possibilities are provided for the ADCs (external, cascaded |
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start pulse of the ADCs. | DRAFT DRAFT | |||||
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The PWMs can be used to generate waveforms in which the frequency, duty cycle and |
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rising and falling edges can be controlled very precisely. Capture inputs are provided to |
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measure event phases compared to the main counter. Depending on the applications, |
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these inputs can be connected to digital sensor motor outputs or digital external signals. |
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Interrupt signals are generated on several events to closely interact with the CPU.
The ADCs can be used for any application needing accurate digitized data from analog sources. To support applications like motor control, a mechanism to synchronize several PWMs and ADCs is available (sync_in and sync_out).
Note that the PWMs run on the PWM clock and the ADCs on the ADC clock, see
Section 8.8.4.
ADC2 IN[7:0] |
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ADC2_EXT_START |
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ADC1 IN[7:0] |
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ADC1_EXT_START |
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ADC clock |
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| MSCSS |
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AHB | VPB sub system bus | SYNCS | 3.3 V | 2 |
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system bus | (to all sub blocks) |
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AHB2VPB |
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BRIDGE |
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| TIMER 1 | 0 | PWM1 MAT[5:0] |
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| PWM | 1 | PWM2 MAT[5:0] |
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| 2 | PWM3 MAT[5:0] |
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PWM0 TRAP |
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PWM0 CAP[2:0] |
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PWM1 TRAP |
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PWM1 CAP[2:0] |
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PWM2 TRAP |
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PWM2 CAP[2:0] |
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PWM3 TRAP |
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PWM3 CAP[2:0] |
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Fig 7. Modulation and sampling control subsystem block diagram |
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8.7.2.1Synchronization and trigger features of the MSCSS
The MSCSS contains two internal timers to generate synchronization and carrier pulses for the ADCs and PWMs. Figure 8 shows how the timers are connected to the ADC and PWM modules.
LPC2917_19_1 | © NXP B.V. 2007. All rights reserved. |
Preliminary data sheet | Rev. 1.01 — 15 November 2007 | 32 of 68 |
