NXP Semiconductors General-purpose I/O, 8.4.6.1, Overview, Description, DLPC2917/19

NXP Semiconductors

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	RAFT	RAFT AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

		DRA	DRA			DR
		F		F
8.4.6	General-purpose I/O	T DRAFT		T
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8.4.6.1	Overview
				DRAFT
	The LPC2917/19 contains four general-purpose I/O ports located at different peripheralDRAFT
						D
	base addresses. In the 144-pin package all four ports are available. All I/O pins are
	bi-directional, and the direction can be programmed individually. The I/O pad behavior DRAFT
	depends on the configuration programmed in the port function-select registers.				DRA

The key features are:

• General-purpose parallel inputs and outputs

• Direction control of individual bits

• Synchronized input sampling for stable input-data values

• All I/O defaults to input at reset to avoid any possible bus conflicts

8.4.6.2 Description

The general-purpose I/O provides individual control over each bi-directional port pin. There are two registers to control I/O direction and output level. The inputs are synchronized to achieve stable read-levels.

To generate an open-drain output, set the bit in the output register to the desired value. Use the direction register to control the signal. When set to output, the output driver actively drives the value on the output: when set to input the signal floats and can be pulled up internally or externally.

8.4.6.3 GPIO pin description

The five GPIO ports in the LPC2917/19 have the pins listed below. The GPIO pins are combined with other functions on the port pins of the LPC2917/19. Table 17 shows the GPIO pins.

Table 17. GPIO pins

Symbol	Direction	Description
GPIO0 pin[31:0]	in/out	GPIO port x pins 31 to 0
GPIO1 pin[31:0]	in/out	GPIO port x pins 31 to 0
GPIO2 pin[27:0]	in/out	GPIO port x pins 27 to 0
GPIO3 pin[15:0]	in/out	GPIO port x pins 15 to 0

8.4.6.4GPIO clock description

The GPIO modules are clocked by several clocks, all of which are derived from

BASE_SYS_CLK; CLK_SYS_PESS and CLK_SYS_GPIOx (x = 0-3), see Section 7.2.2. Note that each GPIO has its own CLK__SYS_GPIOx branch clock for power management. The frequency of all clocks CLK_SYS_GPIOx is identical to CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK.

LPC2917_19_1 © NXP B.V. 2007. All rights reserved.

Preliminary data sheet Rev. 1.01 — 15 November 2007 29 of 68