NXP Semiconductors LPC2919 Description, DLPC2917/19, Raft Aft, T Draft, NXP Semiconductors

NXP Semiconductors

DRAFT	D	D		AFT
	RAFT	RAFT AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T DRAFT	T
DRA	DRA	DR
F	F

•Generation of 10 and 2 test-base clocks, selectable from several embeddedDRAFTclockDRAFT sources

•Crystal oscillator with power-downDRAFT DRAFT

•Control PLL with power-downD

•Very low-power ring oscillator, always on to provide a ’safe clock’DRAFT

•Seven fractional clock dividers with L/D divisionDRA

•Individual source selector for each base clock, with glitch-free switching

•Autonomous clock-activity detection on every clock source

•Protection against switching to invalid or inactive clock sources

•Embedded frequency counter

•Register write-protection mechanism to prevent unintentional alteration of clocks DRAF

Remark: Any clock-frequency adjustment has a direct impact on the timing of on-board peripherals such as the UARTs, SPI, watchdog, timers, CAN controller, LIN master controller, ADCs or flash-memory interface.

8.8.4.2Description

The clock generation unit provides 10 internal clock sources as described in Table 23.

Table 23. CGU base clocks

Number	Name	Frequency	Description
		(MHz) [1]
0	BASE_SAFE_CLK	0.4	Base safe clock (always on)
1	BASE_SYS_CLK	80	Base system clock
2	BASE_PCR_CLK	0.4 [2]	Base PCR subsystem clock
3	BASE_IVNSS_CLK	80	Base IVNSS subsystem clock
4	BASE_MSCSS_CLK	80	Base MSCSS subsystem clock
5	BASE_UART_CLK	80	Base UART clock
6	BASE_SPI_CLK	40	Base SPI clock
7	BASE_TMR_CLK	80	Base timers clock
8	BASE_ADC_CLK	4.5	Base ADCs clock

[1]Maximum frequency that guarantees stable operation of the LPC2917/19.

[2]Fixed to low-power oscillator.

For generation of these base clocks, the CGU consists of primary and secondary clock generators and one output generator for each base clock.

LPC2917_19_1 © NXP B.V. 2007. All rights reserved.

Preliminary data sheet Rev. 1.01 — 15 November 2007 42 of 68