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NXP Semiconductors LPC2919 user manual DLPC2917/19, LQFP144 pin, Draft

Models: LPC2917 LPC2919

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LQFP144 pin

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

Table 3.

Symbol

P0.0

VSS(IO)

P0.1

P0.2

P0.3

P3.0

P3.1

P2.12

P2.13

P0.4

P0.5

VDD(IO)

P0.6

P0.7

VDD(A3V3)

JTAGSEL

NC

VREFP

VREFN

P0.8

P0.9

P0.10

P0.11

P2.14

P2.15

P3.2

VSS(IO)

P3.3

P0.12

P0.13

P0.14

P0.15

P0.16

P0.17

VDD(CORE)

VSS(CORE)

P2.16

P2.17

VDD(IO)

				T DRAFT				T
				DRA			DRA			DR
				F			F
Pin	Description			DRAFT		DRAFT DRAF
LQFP144 pin	assignment …continued
								DRAFT
	Function 0 (default)	Function 1	Function 2	Function 3	DRAFT			DRAFT
	Function 0 (default)	Function 1	Function 2	Function 3
93	GPIO 0, pin 0	-	CAN0 TxD	EXTBUS D24			DRAFT			D
94	ground for I/O						DRAFT
94	ground for I/O
95	GPIO 0, pin 1	-	CAN0 RxD	EXTBUS D25					DRA
96	GPIO 0, pin 2	-	PWM0 MAT0	EXTBUS D26					DRA
96	GPIO 0, pin 2	-	PWM0 MAT0	EXTBUS D26
97	GPIO 0, pin 3	-	PWM0 MAT1	EXTBUS D27
98	GPIO 3, pin 0	-	PWM2 MAT0	EXTBUS CS6
99	GPIO 3, pin 1	-	PWM2 MAT1	EXTBUS CS7
100	GPIO 2, pin 12	-	PWM0 MAT4	SPI0 SDI
101	GPIO 2, pin 13	-	PWM0 MAT5	SPI0 SDO
102	GPIO 0, pin 4	-	PWM0 MAT2	EXTBUS D28
103	GPIO 0, pin 5	-	PWM0 MAT3	EXTBUS D29
104	3.3 V power supply for I/O
105	GPIO 0, pin 6	-	PWM0 MAT4	EXTBUS D30
106	GPIO 0, pin 7	-	PWM0 MAT5	EXTBUS D31

1073.3 V power supply for AD Converters

108TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects boundary scan and flash programming; pulled up internally

109-

110HIGH reference for AD Converters

111LOW reference for AD Converters

112	GPIO 0, pin 8	ADC1 IN0	LIN0 TxD	EXTBUS A20
113	GPIO 0, pin 9	ADC1 IN1	LIN0 RxD	EXTBUS A21
114	GPIO 0, pin 10	ADC1 IN2	PWM1 MAT0	EXTBUS A8
115	GPIO 0, pin 11	ADC1 IN3	PWM1 MAT1	EXTBUS A9
116	GPIO 2, pin 14	-	PWM0 CAP0	EXTBUS BLS0
117	GPIO 2, pin 15	-	PWM0 CAP1	EXTBUS BLS1
118	GPIO 3, pin 2	TIMER3 MAT0	PWM2 MAT2	-
119	ground for I/O
120	GPIO 3, pin 3	TIMER3 MAT1	PWM2 MAT3	-
121	GPIO 0, pin 12	ADC1 IN4	PWM1 MAT2	EXTBUS A10
122	GPIO 0, pin 13	ADC1 IN5	PWM1 MAT3	EXTBUS A11
123	GPIO 0, pin 14	ADC1 IN6	PWM1 MAT4	EXTBUS A12
124	GPIO 0, pin 15	ADC1 IN7	PWM1 MAT5	EXTBUS A13
125	GPIO 0, pin 16	ADC2 IN0	UART0 TXD	EXTBUS A22
126	GPIO 0, pin 17	ADC2 IN1	UART0 RXD	EXTBUS A23

1271.8 V power supply for digital core

128ground for digital core

129	GPIO 2, pin 16	UART1 TxD	PWM0 CAP2	EXTBUS BLS2
130	GPIO 2, pin 17	UART1 RxD	PWM1 CAP0	EXTBUS BLS3
131	3.3 V power supply for I/O

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

9 of 68

Image 9

NXP Semiconductors LPC2919 user manual DLPC2917/19, LQFP144 pin, Draft

Contents

1. Introduction 2. General descriptionLPC2917/19 T DRAFT DLPC2917/19DLPC2917/19 3. FeaturesDLPC2917/19 4. Ordering informationDRA DR 5. Block diagramDRAFT DRAFT Preliminary data sheet6.2.1 General description 6. Pinning information6.2.2 LQFP144 pin assignment DLPC2917/19Function 0 default SymbolDLPC2917/19 RAFT AFTFunction 0 default SymbolDLPC2917/19 RAFT AFTDLPC2917/19 LQFP144 pinDRAFT 7.1.1 Reset and power-up behavior 7.1 Reset, debug, test and power description7.1.2 Reset strategy 7. Functional description7.1.4 Power supply pins description 7.1.3 IEEE 1149.1 interface pins JTAG boundary-scan test7.2.1 Clock architecture DLPC2917/19Preliminary data sheet DRAFDLPC2917/19 RAFT AFTDLPC2917/19 7.2.2 Base clock and branch clock relationshipDRAFT DRAFT DRAF Table 7. Base clock and branch clock overview8. Block description 8.1.1 OverviewDLPC2917/19 DLPC2917/19 8.1.2 Description8.1.4 Flash memory controller clock description 8.1.3 Flash memory controller pin description8.1.5 Flash layout DLPC2917/19DLPC2917/19 8.1.6 Flash bridge wait-statesDRAFT DRAFT Table 9. Flash sector overview …continued8.2.1 Overview 8.2.2 DescriptionDLPC2917/19 8.2.3 External static-memory controller pin description 8.2.5 External memory timing diagrams8.2.4 External static-memory controller clock description Table 12. External memory controller pinsDRAFT DRAFT DRAF DRAFT DRAFTPreliminary data sheet DLPC2917/19RAFT AFT DLPC2917/19T DRAFT NXP Semiconductors8.3.1 General subsystem clock description 8.3.2 Chip and feature identification8.3.3 System Control Unit SCU 8.3.4 Event routerDLPC2917/19 8.4.1 Peripheral subsystem clock description8.4.2.4 Watchdog timer clock description 8.4.3 Timer8.4.2.1 Overview 8.4.2.2 DescriptionDescription 8.4.3.28.4.3.3 Pin description8.4.4 UARTs 8.4.3.4 Timer clock description8.4.4.1 Overview 8.4.4.2 Description8.4.4.4 UART clock description 8.4.5 Serial peripheral interface8.4.5.1 Overview 8.4.5.2 Functional description8.4.5.4 SPI pin description 8.4.5.3 Modes of operation8.4.5.5 SPI clock description DLPC2917/19General-purpose I/O 8.4.68.4.6.1 OverviewOverview 8.5.18.5.2 Global acceptance filter 8.5.3 CAN pin description8.7.1 Overview 8.6.2 LIN pin description8.7.2 Description DLPC2917/19DLPC2917/19 8.7.2.1 Synchronization and trigger features of the MSCSSDLPC2917/19 start ADC conditions is validRAFT AFT T DRAFT8.7.4 MSCSS clock description 8.7.3 MSCSS pin descriptionDLPC2917/19 The MSCSS is clocked from a number of different sources8.7.5.1 Overview 8.7.5 Analog-to-digital converter8.7.5.2 Description DLPC2917/19DLPC2917/19 8.7.5.3 ADC pin descriptionRAFT AFT T DRAFT8.7.5.4 ADC clock description 8.7.6 PWM8.7.6.1 Overview 8.7.6.2 Description8.7.6.3 Synchronizing the PWM counters Fig 10. PWM block diagramDLPC2917/19 8.7.6.4 Master and slave mode 8.7.7 Timers in the MSCSS8.7.6.5 PWM pin description 8.7.6.6 PWM clock description8.8.1 Overview 8.7.7.4 MSCSS timer-clock description8.8.2 Description 8.7.7.2 Description8.8.4 Clock Generation Unit CGU 8.8.3 PCR subsystem clock descriptionPower, Clock & Reset DLPC2917/19DLPC2917/19 8.8.4.2 DescriptionRAFT AFT T DRAFTRAFT AFT DLPC2917/19DRA DR T DRAFTDLPC2917/19 DRAFT DRAFT DRAFLPOSC/crystal Oscillator DLPC2917/19 8.8.4.3 PLL functional descriptionRAFT AFT T DRAFTTriple output phases 8.8.4.4 CGU pin descriptionDirect output mode Power-down control8.8.5.1 Overview 8.8.5 Reset Generation Unit RGU8.8.5.2 Description DLPC2917/198.8.5.3 RGU pin description 8.8.6 Power Management Unit PMU8.8.6.1 Overview 8.8.6.2 DescriptionDRAFT DRAFT DRAFTDRAF Implemented Switch On/Off8.9.1 Overview 8.9 Vectored interrupt controller8.9.2 Description DRAFT DRAFT8.9.3 VIC pin description 9. Limiting values8.9.4 VIC clock description DLPC2917/19DRAFTmA 10. Thermal characteristicsDRAFT SymbolSymbol 11. Static characteristicsDLPC2917/19 RAFT AFTDRAFT DRAFTUnitTable 30. Static characteristics …continued SymbolTable 30. Static characteristics …continued 12. Dynamic characteristicsSymbol SymbolDLPC2917/19 UnitDRAFTDRAFT DRAFT DRAFTSymbol Table 31. Dynamic characteristics …continuedJitter Specification DLPC2917/19Preliminary data sheet 13. Package outlineDLPC2917/19 RAFT AFT14.1 Introduction 14. Soldering14.2 Through-hole mount packages 14.3 Surface mount packagesDLPC2917/19 14.3.2 Wave solderingDRAFT DRAFT MSL Moisture Sensitivity LevelDLPC2917/19 14.3.3 Manual solderingPackage1 DLPC2917/19Soldering method DippingDLPC2917/19 15. AbbreviationsRAFT AFT DRA DRDLPC2917/19 16. ReferencesRAFT AFT DRA DRDLPC2917/19 17. Revision historyDRAFT DRAFT DRAF Table 36. Revision history19. Contact information 18. Legal informationDLPC2917/19 For sales office addresses, send an email to salesaddresses@nxp.com20. Contents continuedDLPC2917/19 9 Limiting values 10 Thermal characteristics T DRAFT11 Static characteristics 12 Dynamic characteristics 19 Contact information 20 Contents