NXP Semiconductors LPC2919 External static-memory controller pin description, DLPC2917/19

NXP Semiconductors

DRAFT	D	D		AFT
	RAFT	RAFT AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

Table 11. External static-memory controller banks

CS[2:0]	Bank
000	bank 0
001	bank 1
010	bank 2

T DRAFT	T
DRA	DRA DR
F	F
DRAFT DRAFT DRAF
DRAFT DRAFT
	DRAFT	D

011 bank 3

100bank 4

101bank 5

110bank 6

111bank 7

DRA

8.2.3External static-memory controller pin description

The external static-memory controller module in the LPC2917/19 has the following pins, which are combined with other functions on the port pins of the LPC2917/19. Table 12 shows the external memory controller pins.

Table 12. External memory controller pins

Symbol	Direction	Description
EXTBUS CSx	out	memory-bank x select, x runs from 0 to 7
EXTBUS BLSy	out	byte-lane select input y, y runs from 0 to 3
EXTBUS WE_N	out	write enable (active LOW)
EXTBUS OE_N	out	output enable (active LOW)
EXTBUS A[23:0]	out	address bus
EXTBUS D[31:0]	in/out	data bus

8.2.4External static-memory controller clock description

The External Static-Memory Controller is clocked by CLK_SYS_SMC, see Section 7.2.2.

8.2.5External memory timing diagrams

A timing diagram for reading from external memory is shown in Figure 4. The relationship between the wait-state settings is indicated with arrows.

LPC2917_19_1 © NXP B.V. 2007. All rights reserved.

Preliminary data sheet Rev. 1.01 — 15 November 2007 19 of 68