NXP Semiconductors DLPC2917/19, UnitDRAFT, Raft Aft, NXP Semiconductors, Draft Draft

NXP Semiconductors

DRAFT	D	D		AFT
	RAFT	RAFT AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T

DRAFT

T

DRA

DRA

DR

DD(CORE)

DD(OSC_PLL)

DD(IO)

DD(A3V3)

vj

F

F

V

= V

DRAFT DRAFT

DRAF

; V

= 2.7 V to 3.6 V; V

= 3.0 V to 3.6 V; T = −40

°C; all voltages are measured with

Table 31. Dynamic characteristics …continued

respect to ground; positive currents flow into the IC; unless otherwise specified.

UnitDRAFT

DRAFT

Symbol

Parameter

Conditions

Min

Typ

Max

ta(W)int

Internal write-access

-

-

24.9

ns

DRAFT

D

time.

UART

fUART	UART frequency.	1⁄65024fclk(uart) -	1⁄2fclk(uart) MHz
SPI

DRA

fSPI	SPI operating	Master operation.	1⁄65024fclk(spi)	-	1⁄2fclk(spi)	MHz
	frequency.
		Slave operation.	1⁄65024fclk(spi)	-	1⁄4fclk(spi)	MHz
Jitter Specification
CANtjit(cc)(p-p)	CAN TXD pin	[2]	-	0.4	1	ns
	Cycle-to-cycle jitter

(peak-to-peak value).

[1]All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 °C ambient temperature on wafer level. Cased products are tested at Tamb = 25 °C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range.

[2]This parameter is not part of production testing or final testing, hence only a typical value is stated.

[3]Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully stable.

[4]Duty cycle clock should be as close as possible to 50%.

LPC2917_19_1 © NXP B.V. 2007. All rights reserved.

Preliminary data sheet Rev. 1.01 — 15 November 2007 57 of 68