NXP Semiconductors DLPC2917/19, Raft Aft, Dra Dr, T Draft, NXP Semiconductors, Draft Draft

NXP Semiconductors

DRAFT	D	D		AFT
	RAFT	RAFT AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T DRAFT		T
DRA	DRA DR
F	F
		DRAF
DRAFT DRAFT

Clock Source Bus			DRAFT DRAFT
LP_OSC
			DRAFT	D
Xtal	FDIV0	OUT 0	DRA
PLL
Oscilator
	FDIV1	OUT 1
	FDIV6	OUT 9
Frequency	Clock
Monitor	Detection
	DTL MMIO Interface

Fig 12. Block diagram of the CGU

There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a crystal oscillator. See Figure 12.

LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU itself and for BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog timer). To prevent the device from losing its clock source LP_OSC cannot be put into power-down. The crystal oscillator can be used as source for high-frequency clocks or as an external clock input if a crystal is not connected.

Secondary clock generators are a PLL and seven fractional dividers (FDIV0..6). The PLL has three clock outputs: normal, 120° phase-shifted and 240° phase-shifted.

Configuration of the CGU: For every output generator - generating the base clocks - a choice can be made from the primary and secondary clock generators according to Figure 13.

LPC2917_19_1 © NXP B.V. 2007. All rights reserved.

Preliminary data sheet Rev. 1.01 — 15 November 2007 43 of 68