TIMER2 MAT2 PWM TRAP1, SPI1 SCK, Rstn | NXP Semiconductors LPC2919

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

Table 3. LQFP144 pin assignment …continued

Symbol	Pin	Description
		Function 0 (default)		Function 1		Function 2
		Function 0 (default)		Function 1		Function 2
VDD(IO)	53	3.3 V power supply for I/O
P2.2	54	GPIO 2, pin 2		TIMER2 MAT2		PWM TRAP1
P2.3	55	GPIO 2, pin 3		TIMER2 MAT3		PWM TRAP0
P1.11	56	GPIO 1, pin 11		SPI1 SCK	-
P1.10	57	GPIO 1, pin 10		SPI1 SDI	-
P3.12	58	GPIO 3, pin 12		SPI1 SCS0		EXTINT4
VSS(CORE)	59	ground for digital core
VDD(CORE)	60	1.8 V power supply for digital core
P3.13	61	GPIO 3, pin 13		SPI1 SDO		EXTINT5
P2.4	62	GPIO 2, pin 4		TIMER1 MAT0		EXTINT0
P2.5	63	GPIO 2, pin 5		TIMER1 MAT1		EXTINT1
P1.9	64	GPIO 1, pin 9		SPI1 SDO		LIN1 RxD
VSS(IO)	65	ground for I/O
P1.8	66	GPIO 1, pin 8		SPI1 SCS0		LIN1 TxD
P1.7	67	GPIO 1, pin 7		SPI1 SCS3		UART1 RxD
P1.6	68	GPIO 1, pin 6		SPI1 SCS2		UART1 TxD
P2.6	69	GPIO 2, pin 6		TIMER1 MAT2		EXTINT2
P1.5	70	GPIO 1, pin 5		SPI1 SCS1		PWM3 MAT5
P1.4	71	GPIO 1, pin 4		SPI2 SCS2		PWM3 MAT4
TRSTN	72	IEEE 1149.1 test reset NOT; active LOW; pulled up internally
RSTN	73	asynchronous device reset; active LOW; pulled up internally
VSS(OSC)	74	ground for oscillator
XOUT_OSC	75	crystal out for oscillator
XIN_OSC	76	crystal in for oscillator
VDD(OSC)	77	1.8 V supply for oscillator
VSS(PLL)	78	ground for PLL
P2.7	79	GPIO 2, pin 7		TIMER1 MAT3		EXTINT3
P3.14	80	GPIO 3, pin 14		SPI1 SDI		EXTINT6
P3.15	81	GPIO 3, pin 15		SPI1 SCK		EXTINT7
VDD(IO)	82	3.3 V power supply for I/O
P2.8	83	GPIO 2, pin 8	-			PWM0 MAT0
P2.9	84	GPIO 2, pin 9	-			PWM0 MAT1
P1.3	85	GPIO 1, pin 3		SPI2 SCS1		PWM3 MAT3
P1.2	86	GPIO 1, pin 2		SPI2 SCS3		PWM3 MAT2
P1.1	87	GPIO 1, pin 1		EXTINT1		PWM3 MAT1
VSS(CORE)	88	ground for digital core
VDD(CORE)	89	1.8 V power supply for digital core
P1.0	90	GPIO 1, pin 0		EXTINT0		PWM3 MAT0
P2.10	91	GPIO 2, pin 10	-			PWM0 MAT2
P2.11	92	GPIO 2, pin 11	-			PWM0 MAT3

T DRAFT		T
DRA		DRA		DR
F		F
DRAFT DRAFT DRAF
Function 3	DRAFT DRAFT
Function 3
		DRAFT		D
EXTBUS D10		DRAFT
EXTBUS D10
EXTBUS D11			DRA
EXTBUS CS3			DRA
EXTBUS CS3

EXTBUS CS2

-

-

EXTBUS D12

EXTBUS D13

EXTBUS CS1

EXTBUS CS0

EXTBUS A7

EXTBUS A6

EXTBUS D14

EXTBUS A5

EXTBUS A4

EXTBUS D15

CAN0 TxD

CAN0 RxD

SPI0 SCS2

SPI0 SCS1

EXTBUS A3

EXTBUS A2

EXTBUS A1

EXTBUS A0

SPI0 SCS0

SPI0 SCK

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

8 of 68

Image 8

NXP Semiconductors LPC2919 TIMER2 MAT2 PWM TRAP1, TIMER2 MAT3 PWM TRAP0, SPI1 SCK, SPI1 SDI, SPI1 SCS0 EXTINT4, SPI1 SDO

Contents

Introduction General descriptionAbout this document Intended audience On-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Ordering information Ordering optionsOrdering information Part options Block diagram LPC2917/19 block diagram Pinning information PinningPin description General description Symbol Pin Description Function 0 default LQFP144 pin assignment … TIMER2 MAT2 PWM TRAP1 TIMER2 MAT3 PWM TRAP0TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1 LQFP144 pin SymbolPin Description Reset, debug, test and power description Reset and power-up behaviorReset strategy Reset pin Ieee 1149.1 interface pins Jtag boundary-scan test Power supply pins descriptionClocking strategy Clock architecture LPC2917/19 block diagram, overview of clock areas LPC2917/19 Base clock and branch clock relationship Base clock and branch clock overviewBase clock Branch clock name Parts of the device clocked by This branch clock Block description Flash memory controllerOverview Base clock DRA Description Flash layout Flash memory controller pin descriptionFlash memory controller clock description Flash bridge wait-states Flash sector overview … External memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External memory timing diagrams External memory controller pinsExternal static-memory controller pin description External static-memory controller clock description Reading from external memory Writing to external memory Reading/writing external memory Chip and feature identification General subsystemGeneral subsystem clock description System Control Unit SCU Symbol Direction Bit position Description Default Polarity Peripheral subsystemPeripheral subsystem clock description Event-router pin connections Pin description TimerWatchdog timer clock description 3.2 Description 3.3 Pin description Timer clock description Timer pinsUart pins UARTs Functional description Serial peripheral interfaceUart clock description SPI pins Modes of operationSPI pin description SPI clock description Gpio pins General-purpose I/O6.1 Overview Gpio pin description Can pins Can gatewayLIN Global acceptance filter LIN controller pins Modulation and sampling control subsystemLIN pin description LIN0/1 Txdl Synchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagram Start ADC conditions is valid Mscss pin description Mscss clock description Draft Analog-to-digital converter ADC pin description ADC block diagramAnalog to digital converter pins 6 PWM ADC clock description PWM block diagram Synchronizing the PWM counters Timers in the Mscss Master and slave modePWM pins PWM pin description Power, clock and reset control subsystem Mscss timer-clock descriptionMscss timer 1 pin Pause pin for Mscss timer Clock Generation Unit CGU Pcrss block diagramPCR subsystem clock description CGU base clocks Number Name Frequency Description MHz Block diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset Generation Unit RGU Reset output configuration RGU pin description Power Management Unit PMURGU pins DRA Vectored interrupt controller PMU pin description VIC clock description Limiting valuesVIC pin description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as input Analog-to-digital converter supply VDDA5V FSRINL LSB Dynamic characteristics Power-up resetDynamic characteristics Symbol Parameter Conditions Min Typ Max Unit UnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Package outline Package outline SOT486-1 LQFP144 Soldering IntroductionThrough-hole mount packages Surface mount packages Volume mm3 350 235 220 Lead-free process from J-STD-020C Temperature profiles for large and small componentsWave soldering SnPb eutectic process from J-STD-020C Package thickness mm Package related soldering information Mounting Package1 Soldering method Wave Reflow2 DippingCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SIL Mounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact information Contents Package outline Contact information ContentsSoldering