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NXP Semiconductors LPC2919 DRAFTUnit, Draft, DLPC2917/19, Raft Aft, NXP Semiconductors, Symbol

Models: LPC2917 LPC2919

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Table 30. Static characteristics …continued

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T

DRAFT

T

DRA

DRA

DR

DD(CORE)

DD(OSC_PLL)

DD(IO)

DD(A3V3)

vj

F

F

V

= V

= 3.0 V to 3.6 V; T

= -40 °C to +125

DRAFT DRAFT

DRAF

; V

= 2.7 V to 3.6 V; V

°C; all voltages are

Table 30. Static characteristics …continued

measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1]

DRAFTUnit

DRAFT

Symbol

Parameter

Conditions

Min

Typ

Max

ILIL

LOW-state input leakage

-

-

1

μA

DRAFT

D

current.

II(pd)	Pull-down input current. All port pins, VI = 3.3 V;	25	50	100	μA
	VI = 5.5 V.

DRA

II(pu)

Pull-up input current.

All port pins, RESET_N, −25−50 −100 μA TRST_N, TDI,

JTAGSEL, TMS: VI = 0 V; VI > 3.6 V is not allowed.

Ci	Input capacitance.		[3] -	3	8	pF
Output pins and I/O pins configured as output

VO	Output voltage.		0	-	VDD(IO)	V

VOH	HIGH-state output	IOH = −4 mA	VDD(IO) – 0.4	-	-	V
	voltage.
VOL	LOW-state output voltage. IOL = 4 mA		-	-	0.4	V
CL	Load capacitance.		-	-	25	pF
Analog-to-digital converter supply

VVREFN	Voltage on pin VREFN.		0	-	VVREFP − 2	V
VVREFP	Voltage on pin VREFP.		VVREFN + 2	-	VDD(A3V3)	V
VI(ADC)	ADC input voltage on	Port 0.	VVREFN	-	VVREFP	V
	port 0 pins
Zi	Input impedance.	Between VREFN and	4.4	-	-	kΩ
		VREFP
		Between VREFN and	13.7	-	23.6	kΩ
		VDD(A5V)
FSR	Full scale range.		2	-	10	bit

INL	Integral non-linearity.		−1	-	+1	LSB

DNL	Differential non-linearity.		−1	-	+1	LSB

Verr(offset)	Offset error voltage.		−20	-	+20	mV
Verr(FS)	Full-scale error voltage.		−20	-	+20	mV

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

54 of 68

Image 54

NXP Semiconductors LPC2919 DRAFTUnit, DLPC2917/19, Raft Aft, NXP Semiconductors, Draft Draft, Symbol, Parameter

Contents

1. Introduction 2. General descriptionLPC2917/19 DLPC2917/19 T DRAFT3. Features DLPC2917/194. Ordering information DLPC2917/19DRAFT DRAFT 5. Block diagramDRA DR Preliminary data sheet6.2.2 LQFP144 pin assignment 6. Pinning information6.2.1 General description DLPC2917/19DLPC2917/19 SymbolFunction 0 default RAFT AFTDLPC2917/19 SymbolFunction 0 default RAFT AFTDLPC2917/19 LQFP144 pinDRAFT 7.1.2 Reset strategy 7.1 Reset, debug, test and power description7.1.1 Reset and power-up behavior 7. Functional description7.2.1 Clock architecture 7.1.3 IEEE 1149.1 interface pins JTAG boundary-scan test7.1.4 Power supply pins description DLPC2917/19DLPC2917/19 DRAFPreliminary data sheet RAFT AFTDRAFT DRAFT DRAF 7.2.2 Base clock and branch clock relationshipDLPC2917/19 Table 7. Base clock and branch clock overview8. Block description 8.1.1 OverviewDLPC2917/19 8.1.2 Description DLPC2917/198.1.5 Flash layout 8.1.3 Flash memory controller pin description8.1.4 Flash memory controller clock description DLPC2917/19DRAFT DRAFT 8.1.6 Flash bridge wait-statesDLPC2917/19 Table 9. Flash sector overview …continued8.2.1 Overview 8.2.2 DescriptionDLPC2917/19 8.2.4 External static-memory controller clock description 8.2.5 External memory timing diagrams8.2.3 External static-memory controller pin description Table 12. External memory controller pinsPreliminary data sheet DRAFT DRAFTDRAFT DRAFT DRAF DLPC2917/19T DRAFT DLPC2917/19RAFT AFT NXP Semiconductors8.3.3 System Control Unit SCU 8.3.2 Chip and feature identification8.3.1 General subsystem clock description 8.3.4 Event router8.4.1 Peripheral subsystem clock description DLPC2917/198.4.2.1 Overview 8.4.3 Timer8.4.2.4 Watchdog timer clock description 8.4.2.2 Description8.4.3.3 8.4.3.2Description Pin description8.4.4.1 Overview 8.4.3.4 Timer clock description8.4.4 UARTs 8.4.4.2 Description8.4.5.1 Overview 8.4.5 Serial peripheral interface8.4.4.4 UART clock description 8.4.5.2 Functional description8.4.5.5 SPI clock description 8.4.5.3 Modes of operation8.4.5.4 SPI pin description DLPC2917/198.4.6.1 8.4.6General-purpose I/O Overview8.5.2 Global acceptance filter 8.5.1Overview 8.5.3 CAN pin description8.7.2 Description 8.6.2 LIN pin description8.7.1 Overview DLPC2917/198.7.2.1 Synchronization and trigger features of the MSCSS DLPC2917/19RAFT AFT start ADC conditions is validDLPC2917/19 T DRAFTDLPC2917/19 8.7.3 MSCSS pin description8.7.4 MSCSS clock description The MSCSS is clocked from a number of different sources8.7.5.2 Description 8.7.5 Analog-to-digital converter8.7.5.1 Overview DLPC2917/19RAFT AFT 8.7.5.3 ADC pin descriptionDLPC2917/19 T DRAFT8.7.6.1 Overview 8.7.6 PWM8.7.5.4 ADC clock description 8.7.6.2 Description8.7.6.3 Synchronizing the PWM counters Fig 10. PWM block diagramDLPC2917/19 8.7.6.5 PWM pin description 8.7.7 Timers in the MSCSS8.7.6.4 Master and slave mode 8.7.6.6 PWM clock description8.8.2 Description 8.7.7.4 MSCSS timer-clock description8.8.1 Overview 8.7.7.2 DescriptionPower, Clock & Reset 8.8.3 PCR subsystem clock description8.8.4 Clock Generation Unit CGU DLPC2917/19RAFT AFT 8.8.4.2 DescriptionDLPC2917/19 T DRAFTDRA DR DLPC2917/19RAFT AFT T DRAFTDLPC2917/19 DRAFT DRAFT DRAFLPOSC/crystal Oscillator RAFT AFT 8.8.4.3 PLL functional descriptionDLPC2917/19 T DRAFTPower-down control 8.8.4.4 CGU pin descriptionTriple output phases DLPC2917/198.8.5.2 Description 8.8.5 Reset Generation Unit RGU8.8.5.1 Overview DLPC2917/198.8.6.1 Overview 8.8.6 Power Management Unit PMU8.8.5.3 RGU pin description 8.8.6.2 DescriptionDRAF DRAFT DRAFTDRAFT Implemented Switch On/Off8.9.2 Description 8.9 Vectored interrupt controller8.9.1 Overview DRAFT DRAFT8.9.4 VIC clock description 9. Limiting values8.9.3 VIC pin description DLPC2917/19DRAFT 10. Thermal characteristicsDRAFTmA SymbolDLPC2917/19 11. Static characteristicsSymbol RAFT AFTTable 30. Static characteristics …continued DRAFTUnitDRAFT SymbolSymbol 12. Dynamic characteristicsTable 30. Static characteristics …continued SymbolDRAFT DRAFT UnitDRAFTDLPC2917/19 DRAFTJitter Specification Table 31. Dynamic characteristics …continuedSymbol DLPC2917/19DLPC2917/19 13. Package outlinePreliminary data sheet RAFT AFT14.2 Through-hole mount packages 14. Soldering14.1 Introduction 14.3 Surface mount packagesDRAFT DRAFT 14.3.2 Wave solderingDLPC2917/19 MSL Moisture Sensitivity Level14.3.3 Manual soldering DLPC2917/19Soldering method DLPC2917/19Package1 DippingRAFT AFT 15. AbbreviationsDLPC2917/19 DRA DRRAFT AFT 16. ReferencesDLPC2917/19 DRA DRDRAFT DRAFT DRAF 17. Revision historyDLPC2917/19 Table 36. Revision historyDLPC2917/19 18. Legal information19. Contact information For sales office addresses, send an email to salesaddresses@nxp.com20. Contents continuedDLPC2917/19 11 Static characteristics 12 Dynamic characteristics T DRAFT9 Limiting values 10 Thermal characteristics 19 Contact information 20 Contents