NXP Semiconductors Dynamic characteristics, DLPC2917/19, DRAFTUnit, Draft, Raft Aft, Symbol

NXP Semiconductors

DRAFT	D	D		AFT
	RAFT	RAFT AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T

DRAFT

T

DRA

DRA

DR

DD(CORE)

DD(OSC_PLL)

DD(IO)

DD(A3V3)

vj

F

F

V

= V

; V

= 3.0 V to 3.6 V; T

= -40 °C to +125

DRAFT DRAFT

DRAF

= 2.7 V to 3.6 V; V

°C; all voltages are

Table 30. Static characteristics …continued

measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1]

DRAFTUnit

DRAFT

Symbol

Parameter

Conditions

Min

Typ

Max

Rs(xtal)

Crystal series resistance.

fosc = 10 MHz to 15 MHz

[5]

DRAFT

D

Oscillator

Cxtal = 10 pF;	-	-	160	Ω
Cext = 18 pF

DRA

		Cxtal = 20 pF;		-	-	60	Ω
		Cext = 39 pF
		fosc = 15 MHz to 20 MHz	[5]
		Cxtal = 10 pF;		-	-	80	Ω
		Cext = 18 pF
Ci	Input capacitance of		[9]	-		2	pF
	XIN_OSC.
Power-up reset
Vtrip(high)	High trip-level voltage.		[6]	1.2	1.4	1.6	V
Vtrip(low)	Low trip-level voltage.		[6]	1.1	1.3	1.5	V
Vtrip(dif)	Difference between high		[6]	50	120	180	mV
	and low trip-level

voltages.

[1]All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 °C on wafer level. Cased products are tested at Tamb = 25 °C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power-supply voltage range.

[2]Leakage current is exponential to temperature; worst-case value is at 125 C Tvj. All clocks off. Analog modules and FLASH powered down.

[3]For Port 0, pin 0 to pin 15 add maximum 1.5 pF for input capacitance to ADC. For Port 0, pin 16 to pin 31 add maximum 1.0 pF for input capacitance to ADC.

[4]This value is the minimum drive capability. Maximum short-circuit output current is 33 mA (drive HIGH-level, shorted to ground) or −38 mA. (drive LOW-level, shorted to VDD(IO)). The device will be damaged if multiple outputs are shorted.

[5]Cxtal is crystal load capacitance and Cext are the two external load capacitors.

[6]The power-up reset has a time filter: VDD(CORE) must be above Vtrip(high) for 2 μs before reset is de-asserted; VDD(CORE) must be below Vtrip(low) for 11 μs before internal reset is asserted.

[7]Not 5 V-tolerant when pull-up is on.

[8]For I/O Port 0, the maximum input voltage is defined by VI(ADC).

[9]This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are based on simulation results.

12. Dynamic characteristics

Table 31. Dynamic characteristics

VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = −40 °C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
I/O pins
tTHL	HIGH-to-LOW	CL = 30 pF	4	-	13.8	ns
	transition time.
tTLH	LOW-to-HIGH	CL = 30 pF	4	-	13.8	ns
	transition time.
LPC2917_19_1					© NXP B.V. 2007. All rights reserved.

Preliminary data sheet Rev. 1.01 — 15 November 2007 55 of 68