NXP Semiconductors LPC2917, LPC2919 Limiting values, VIC pin description, VIC clock description

Models: LPC2917 LPC2919

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8.9.3VIC pin description

NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T

DRAFT

 

T

 

DRA

 

DRA

 

DR

F

 

 

F

 

Interrupt-request masking is performed individually per interrupt target by comparing the

 

DRAF

priority level assigned to a specific interrupt request with a target-specific priorityDRAFT DRAFT

 

 

threshold. The priority levels are defined as follows:

DRAFT DRAFT

 

 

 

 

 

Priority level 0 corresponds to ‘masked’ (i.e. interrupt requests with priority 0 never

 

 

D

lead to an interrupt)

 

DRAFT

 

 

 

 

 

 

Priority 1 corresponds to the lowest priority

 

 

 

DRA

Priority 15 corresponds to the highest priority

 

 

 

 

 

 

 

 

Software interrupt support is provided and can be supplied for:

Testing RTOS interrupt handling without using device-specific interrupt service routines

Software emulation of an interrupt-requesting device, including interrupts

8.9.3VIC pin description

The VIC module in the LPC2917/19 has no external pins.

8.9.4VIC clock description

The VIC is clocked by CLK_SYS_VIC, see Section 7.2.2.

9.Limiting values

Table 28. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

 

Min

Max

Unit

Supply pins

 

 

 

 

 

 

 

 

 

 

 

 

 

Ptot

Total power dissipation.

 

[1]

-

1

W

VDD(CORE)

Core supply voltage.

 

 

0.5

+2.0

V

VDD(OSC_PLL)

Oscillator and PLL supply

 

 

0.5

+2.0

V

 

voltage.

 

 

 

 

 

VDD(ADC3V3)

3.3 V ADC supply voltage.

 

 

0.5

+4.6

V

VDD(IO)

I/O digital supply voltage.

 

 

0.5

+4.6

V

IDD

Supply current.

Average value per supply

[2]

-

98

mA

 

 

pin.

 

 

 

 

 

 

 

 

 

 

 

ISS

Ground current.

Average value per ground

[2]

-

98

mA

 

 

pin.

 

 

 

 

Input pins and I/O pins

 

 

 

 

 

 

 

 

 

 

 

 

VXIN_OSC

Voltage on pin XIN_OSC.

 

 

0.5

+2.0

V

VXIN_RTC

Voltage on pin XIN_RTC.

 

 

0.5

+2.0

V

VI(IO)

I/O input voltage.

 

[3][4][5]

0.5

VDD(IO) + 3.0

V

VI(ADC)

ADC input voltage.

I/O port 0.

[4][5]

0.5

VDD(ADC3V3) + 0.5

V

 

 

 

 

 

 

 

VVREFP

Voltage on pin VREFP.

 

 

0.5

+3.6

V

 

 

 

 

 

 

 

VVREFN

Voltage on pin VREFN.

 

 

0.5

+3.6

V

 

 

 

 

 

 

 

II(ADC)

ADC input current.

Average value per input pin.

[2]

-

35

mA

 

 

 

 

 

Output pins and I/O pins configured as output

 

 

 

 

LPC2917_19_1

 

 

 

 

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

51 of 68

Page 51
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NXP Semiconductors LPC2919 user manual Limiting values, VIC pin description, VIC clock description, DLPC2917/19