Dra, Description | NXP Semiconductors LPC2917, LPC2919 manual

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

	T	DRAFT			T
	DRA		DRA				DR
	F			F
The flash memory has a 128-bit wide data interface and the flash controller offers two						DRAF
128-bit buffer lines to improve system performance. The flash has to be programmedDRAFT DRAFT
initially via JTAG. In-system programming must be supported by the boot loader.				DRAFT
In-application programming is possible. Flash memory contents can be protectedDRAFTby				DRAFT
disabling JTAG access. Suspension of burning or erasing is not supported.			DRAFT				D

The key features are:
The key features are:						DRA
•	Programming by CPU via AHB					DRA
•	Programming by CPU via AHB
• Programming by external programmer via JTAG
•	JTAG access protection
• Burn-finished and erase-finished interrupt
8.1.2 Description
After reset flash initialization is started, which takes tinit time, see Section 12. During this
initialization flash access is not possible and AHB transfers to flash are stalled, blocking
the AHB bus.
During flash initialization the index sector is read to identify the status of the JTAG access
protection and sector security. If JTAG access protection is active the flash is not
accessible via JTAG. ARM debug facilities are disabled to protect the flash-memory
contents against unwanted reading out externally. If sector security is active only the
concerned sections are read.
Flash can be read synchronously or asynchronously to the system clock. In synchronous
operation the flash goes into standby after returning the read data. Started reads cannot
be stopped, and speculative reading and dual buffering are therefore not supported.
With asynchronous reading, transfer of the address to the flash and of read data from the
flash is done asynchronously, giving the fastest possible response time. Started reads can
be stopped, so speculative reading and dual buffering are supported.
Buffering is offered because the flash has a 128-bit wide data interface while the AHB
interface has only 32 bits. With buffering a buffer line holds the complete 128-bit flash
word, from which four words can be read. Without buffering every AHB data port read
starts a flash read. A flash read is a slow process compared to the minimum AHB cycle
time, so with buffering the average read time is reduced. This can improve system
performance.
With single buffering the most recently read flash word remains available until the next
flash read. When an AHB data-port read transfer requires data from the same flash word
as the previous read transfer, no new flash read is done and the read data is given without
wait cycles.
When an AHB data-port read transfer requires data from a different flash word to that
involved in the previous read transfer, a new flash read is done and wait states are given
until the new read data is available.
With dual buffering a secondary buffer line is used, the output of the flash being
considered as the primary buffer. On a primary buffer hit data can be copied to the
secondary buffer line, which allows the flash to start a speculative read of the next flash
word.
LPC2917_19_1	© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

15 of 68

Image 15

NXP Semiconductors LPC2917, LPC2919 user manual Dra, Description

Contents

Intended audience IntroductionGeneral description About this document NXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Part options Ordering informationOrdering options Ordering information LPC2917/19 block diagram Block diagram General description Pinning informationPinning Pin description LQFP144 pin assignment … Symbol Pin Description Function 0 default TIMER1 MAT1 EXTINT1 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT0 EXTINT0 Symbol Pin DescriptionLQFP144 pin Reset pin Reset, debug, test and power descriptionReset and power-up behavior Reset strategy Clock architecture Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clocking strategy LPC2917/19 LPC2917/19 block diagram, overview of clock areas This branch clock Base clock and branch clock relationshipBase clock and branch clock overview Base clock Branch clock name Parts of the device clocked by Base clock Block descriptionFlash memory controller Overview Description DRA Flash memory controller pin description Flash memory controller clock descriptionFlash layout Flash sector overview … Flash bridge wait-states 32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External static-memory controller clock description External memory timing diagramsExternal memory controller pins External static-memory controller pin description Writing to external memory Reading from external memory Reading/writing external memory System Control Unit SCU Chip and feature identificationGeneral subsystem General subsystem clock description Event-router pin connections Symbol Direction Bit position Description Default PolarityPeripheral subsystem Peripheral subsystem clock description Timer Watchdog timer clock descriptionPin description 3.3 Pin description 3.2 Description UARTs Timer clock descriptionTimer pins Uart pins Serial peripheral interface Uart clock descriptionFunctional description SPI clock description SPI pinsModes of operation SPI pin description Gpio pin description Gpio pinsGeneral-purpose I/O 6.1 Overview Global acceptance filter Can pinsCan gateway LIN LIN0/1 Txdl LIN controller pinsModulation and sampling control subsystem LIN pin description Modulation and sampling control subsystem block diagram Synchronization and trigger features of the Mscss Start ADC conditions is valid Mscss clock description Mscss pin description Analog-to-digital converter Draft ADC block diagram Analog to digital converter pinsADC pin description ADC clock description 6 PWM Synchronizing the PWM counters PWM block diagram PWM pin description Timers in the MscssMaster and slave mode PWM pins Pause pin for Mscss timer Power, clock and reset control subsystemMscss timer-clock description Mscss timer 1 pin Pcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocks Block diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset output configuration Reset Generation Unit RGU Power Management Unit PMU RGU pinsRGU pin description DRA PMU pin description Vectored interrupt controller Limiting values VIC pin descriptionVIC clock description Thermal characteristics Input pins and I/O pins configured as input Static characteristicsStatic characteristics Symbol Parameter Conditions Min Typ Max LSB Analog-to-digital converter supplyVDDA5V FSR INL Symbol Parameter Conditions Min Typ Max Unit Dynamic characteristicsPower-up reset Dynamic characteristics UnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter Specification Package outline SOT486-1 LQFP144 Package outline Surface mount packages SolderingIntroduction Through-hole mount packages SnPb eutectic process from J-STD-020C Package thickness mm Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components Wave soldering DBS, DIP, HDIP, RDBS, SDIP, SIL Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping CPGA, Hcpga Mounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Contact information Legal information Contents Contact information Contents SolderingPackage outline