Introduction | NXP Semiconductors LPC2917, LPC2919 instruction

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1. Introduction

ARM9 microcontroller with CAN and LIN

Rev. 1.01 — 15 November 2007

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Preliminary data sheet
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1.1 About this document

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This document lists detailed information about the LPC2917/19 device. It focuses on factual information like pinning, characteristics etc. Short descriptions are used to outline the concept of the features and functions. More details and background on developing applications for this device are given in the LPC2917/19 User Manual (see Ref. 1). No explicit references are made to the User Manual.

1.2 Intended audience

This document is written for engineers evaluating and/or developing systems, hard- and/or software for the LPC2917/19. Some basic knowledge of ARM processors and architecture and ARM968E-S in particular is assumed (see Ref. 2).

2.General description

2.1Architectural overview

The LPC2917/19 consists of:

•An ARM968E-S processor with real-time emulation support

•An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the on-chip memory controllers

•Two DTL buses (a universal NXP interface) for interfacing to the interrupt controller and the Power, Clock and Reset Control cluster (also called subsystem)

•Three VLSI Peripheral Buses (VPB - a compatible superset of ARM's AMBA advanced peripheral bus) for connection to on-chip peripherals clustered in subsystems.

The LPC2917/19 configures the ARM968E-S processor in little-endian byte order. All peripherals run at their own clock frequency to optimize the total system power consumption. The AHB2VPB bridge used in the subsystems contains a write-ahead buffer one transaction deep. This implies that when the ARM968E-S issues a buffered write action to a register located on the VPB side of the bridge, it continues even though the actual write may not yet have taken place. Completion of a second write to the same subsystem will not be executed until the first write is finished.

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NXP Semiconductors LPC2917, LPC2919 user manual Introduction, General description, About this document, Intended audience

Contents

General description IntroductionAbout this document Intended audience ARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Ordering options Ordering informationOrdering information Part options LPC2917/19 block diagram Block diagram Pinning Pinning informationPin description General description LQFP144 pin assignment … Symbol Pin Description Function 0 default TIMER2 MAT3 PWM TRAP0 TIMER2 MAT2 PWM TRAP1TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1 Pin Description SymbolLQFP144 pin Reset and power-up behavior Reset, debug, test and power descriptionReset strategy Reset pin Power supply pins description Ieee 1149.1 interface pins Jtag boundary-scan testClocking strategy Clock architecture LPC2917/19 LPC2917/19 block diagram, overview of clock areas Base clock and branch clock overview Base clock and branch clock relationshipBase clock Branch clock name Parts of the device clocked by This branch clock Flash memory controller Block descriptionOverview Base clock Description DRA Flash memory controller clock description Flash memory controller pin descriptionFlash layout Flash sector overview … Flash bridge wait-states External static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External memory controller pins External memory timing diagramsExternal static-memory controller pin description External static-memory controller clock description Writing to external memory Reading from external memory Reading/writing external memory General subsystem Chip and feature identificationGeneral subsystem clock description System Control Unit SCU Peripheral subsystem Symbol Direction Bit position Description Default PolarityPeripheral subsystem clock description Event-router pin connections Watchdog timer clock description TimerPin description 3.3 Pin description 3.2 Description Timer pins Timer clock descriptionUart pins UARTs Uart clock description Serial peripheral interfaceFunctional description Modes of operation SPI pinsSPI pin description SPI clock description General-purpose I/O Gpio pins6.1 Overview Gpio pin description Can gateway Can pinsLIN Global acceptance filter Modulation and sampling control subsystem LIN controller pinsLIN pin description LIN0/1 Txdl Modulation and sampling control subsystem block diagram Synchronization and trigger features of the Mscss Start ADC conditions is valid Mscss clock description Mscss pin description Analog-to-digital converter Draft Analog to digital converter pins ADC block diagramADC pin description ADC clock description 6 PWM Synchronizing the PWM counters PWM block diagram Master and slave mode Timers in the MscssPWM pins PWM pin description Mscss timer-clock description Power, clock and reset control subsystemMscss timer 1 pin Pause pin for Mscss timer PCR subsystem clock description Pcrss block diagramClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocks Block diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset output configuration Reset Generation Unit RGU RGU pins Power Management Unit PMURGU pin description DRA PMU pin description Vectored interrupt controller VIC pin description Limiting valuesVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as input VDDA5V FSR Analog-to-digital converter supplyINL LSB Power-up reset Dynamic characteristicsDynamic characteristics Symbol Parameter Conditions Min Typ Max Unit UnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter Specification Package outline SOT486-1 LQFP144 Package outline Introduction SolderingThrough-hole mount packages Surface mount packages Temperature profiles for large and small components Volume mm3 350 235 220 Lead-free process from J-STD-020CWave soldering SnPb eutectic process from J-STD-020C Package thickness mm Mounting Package1 Soldering method Wave Reflow2 Dipping Package related soldering informationCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SIL Mounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal information Contents Soldering Contact information ContentsPackage outline