NXP Semiconductors LPC2919 start ADC conditions is valid, DLPC2917/19, Raft Aft, T Draft

NXP Semiconductors

DRAFT	D	D		AFT
	RAFT	RAFT AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

	T DRAFT		T
	DRA		DRA	DR
	F		F
Each ADC module has four start inputs. An ADC conversion is started when one of the				DRAF
start ADC conditions is valid:	DRAFT	DRAFT

•start 0: ADC external start input pin; can be triggered at a positive or negativeDRAFTedge. DRAFT

Note that this signal is captured in the ADC clock domainD

•start 1: If the ‘preceding’ ADC conversion is ended, the sync_out signal starts an ADCDRAFT

conversion. This signal is captured in the MSCSS subsystem clock domain, see DRA Section 8.7.5.2. As can be seen in Figure 8, the sync_out of ADC1 is connected to the

start 1 input of ADC2 and the sync_out of ADC2 is connected to the start 1 input of ADC1.

•start 2: The PWM sync_out can start an ADC conversion. The sync_out signal is synchronized to the ADC clock in the ADC module. This signal is captured in the MSCSS subsystem clock domain.

•start 3: The match outputs from MSCSS timer 0 are connected to the start 3 inputs of the ADCs. This signal is captured in the ADC clock domain.

The PWM_sync and trans_enable_in of PWM 0 are connected to the 4th match output of MSCSS timer 0 to start the PWM after a pre-programmed delay. This sync signal is cascaded through all PWMs, allowing a programmable delay offset between subsequent PWMs. The sync delay of each PWM can be programmed synchronously or with a different phase for spreading the power load.

The match outputs of MSCSS timer 1 (PWM control) are connected to the corresponding carrier inputs of the PWM modules. The carrier signal is modulated with the PWM- generated waveforms.

The pause input of MSCSS timer 1 (PWM Control) is connected to an external input pin.

Generation of the carrier signal is stopped by asserting the pause of this timer.

The pause input of MSCSS timer 0 (ADC Control) is connected to a ‘NOR’ of the PWM_sync outputs (start 2 input on the ADCs). If the pause feature of this timer is enabled the timer only counts when one of the PWM_sync outputs is active HIGH. This feature can be used to start the ADC once every x PWM cycles, where x corresponds to the value in the match register of the timer. In this case the start 3 input of the ADC should be enabled (start on match output of MSCSS timer 0).

The signals connected to the capture inputs of the timers (both MSCSS timer 0 and

MSCSS timer 1) are intended for debugging.

LPC2917_19_1 © NXP B.V. 2007. All rights reserved.

Preliminary data sheet Rev. 1.01 — 15 November 2007 33 of 68