UARTs, Timer clock description | NXP Semiconductors LPC2919 instruction

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

Table 14. Timer pins

Symbol	Direction
TIMERx CAP[0]	IN
TIMERx CAP[1]	IN
TIMERx CAP[2]	IN

Description

TIMER x capture input 0

TIMER x capture input 1

TIMER x capture input 2

T DRAFT	T
DRA	DRA DR
F	F
DRAFT DRAFT DRAF
DRAFT DRAFT
	DRAFT	D
	DRAFT

TIMERx CAP[3]	IN
TIMERx MAT[0]	OUT
TIMERx MAT[1]	OUT
TIMERx MAT[2]	OUT
TIMERx MAT[3]	OUT

	TIMER x capture input 3	DRA
	TIMER x match output 0	DRA
	TIMER x match output 0
	TIMER x match output 1
	TIMER x match output 2
	TIMER x match output 3

8.4.3.4Timer clock description

The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx (x = 0-3), see Section 7.2.2. Note that each timer has its own CLK_TMRx branch clock for power management. The frequency of all these clocks is identical as they are derived from the same base clock BASE_CLK_TMR. The register interface towards the system bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_TMRx.

8.4.4UARTs

8.4.4.1Overview

The LPC2917/19 contains two identical UARTs located at different peripheral base addresses. The key features are:

•16-byte receive and transmit FIFOs

•Registers conform to industry standard 550

•Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes

•Built-in baud-rate generator

8.4.4.2Description

The UART is commonly used to implement a serial interface such as RS232. The LPC2917/19 contains two industry-standard 550 UARTs with 16-byte transmit and receive FIFOs, but they can also be put into 450 mode without FIFOs.

8.4.4.3UART pin description

The two UARTs in the LPC2917/19 have the following pins. The UART pins are combined with other functions on the port pins of the LPC2917/19. Table 15 shows the UART pins (x runs from 0 to 1).

Table 15. UART pins

Symbol	Direction	Description
UARTx TXD	out	UART channel x transmit data output

UARTx RXD	in	UART channel x receive data input

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

26 of 68

Image 26

NXP Semiconductors LPC2919, LPC2917 user manual UARTs, Timer clock description, Uart pin description, Timer pins, Uart pins

Contents

About this document IntroductionGeneral description Intended audience On-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Ordering information Ordering informationOrdering options Part options Block diagram LPC2917/19 block diagram Pin description Pinning informationPinning General description Symbol Pin Description Function 0 default LQFP144 pin assignment … TIMER1 MAT0 EXTINT0 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT1 EXTINT1 LQFP144 pin SymbolPin Description Reset strategy Reset, debug, test and power descriptionReset and power-up behavior Reset pin Clocking strategy Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clock architecture LPC2917/19 block diagram, overview of clock areas LPC2917/19 Base clock Branch clock name Parts of the device clocked by Base clock and branch clock relationshipBase clock and branch clock overview This branch clock Overview Block descriptionFlash memory controller Base clock DRA Description Flash layout Flash memory controller pin descriptionFlash memory controller clock description Flash bridge wait-states Flash sector overview … External memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External static-memory controller pin description External memory timing diagramsExternal memory controller pins External static-memory controller clock description Reading from external memory Writing to external memory Reading/writing external memory General subsystem clock description Chip and feature identificationGeneral subsystem System Control Unit SCU Peripheral subsystem clock description Symbol Direction Bit position Description Default PolarityPeripheral subsystem Event-router pin connections Pin description TimerWatchdog timer clock description 3.2 Description 3.3 Pin description Uart pins Timer clock descriptionTimer pins UARTs Functional description Serial peripheral interfaceUart clock description SPI pin description SPI pinsModes of operation SPI clock description 6.1 Overview Gpio pinsGeneral-purpose I/O Gpio pin description LIN Can pinsCan gateway Global acceptance filter LIN pin description LIN controller pinsModulation and sampling control subsystem LIN0/1 Txdl Synchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagram Start ADC conditions is valid Mscss pin description Mscss clock description Draft Analog-to-digital converter ADC pin description ADC block diagramAnalog to digital converter pins 6 PWM ADC clock description PWM block diagram Synchronizing the PWM counters PWM pins Timers in the MscssMaster and slave mode PWM pin description Mscss timer 1 pin Power, clock and reset control subsystemMscss timer-clock description Pause pin for Mscss timer Clock Generation Unit CGU Pcrss block diagramPCR subsystem clock description CGU base clocks Number Name Frequency Description MHz Block diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset Generation Unit RGU Reset output configuration RGU pin description Power Management Unit PMURGU pins DRA Vectored interrupt controller PMU pin description VIC clock description Limiting valuesVIC pin description Thermal characteristics Symbol Parameter Conditions Min Typ Max Static characteristicsStatic characteristics Input pins and I/O pins configured as input INL Analog-to-digital converter supplyVDDA5V FSR LSB Dynamic characteristics Dynamic characteristicsPower-up reset Symbol Parameter Conditions Min Typ Max Unit UnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Package outline Package outline SOT486-1 LQFP144 Through-hole mount packages SolderingIntroduction Surface mount packages Wave soldering Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components SnPb eutectic process from J-STD-020C Package thickness mm CPGA, Hcpga Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping DBS, DIP, HDIP, RDBS, SDIP, SIL Mounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact information Contents Package outline Contact information ContentsSoldering