Thermal characteristics | NXP Semiconductors LPC2919, LPC2917

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

Table 28. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

T DRAFT	T
DRA	DRA DR
F	F
DRAFT DRAFT DRAF

IOHS	HIGH-state short-circuit	Drive HIGH, output shorted	[9]		-	−33	DRAFTmA	DRAFT
Symbol	Parameter	Conditions			Min	Max	Unit
IOLS	LOW-state short-circuit	Drive LOW, output shorted	[9]		-	+38	mA DRAFT		D
	output current.	to VSS(IO).
	output current.	to VDD(IO).						DRA
	output current.	to VDD(IO).

General

Tstg	Storage temperature.				−40	+150	°C
Tamb	Ambient temperature.				−40	+85	°C
Tvj	Virtual junction temperature.			[6]	−40	+125	°C
Memory

nendu(fl)	Endurance of flash memory.				-	100 000	cycle
tret(fl)	Flash memory retention				-	20	year
	time.
Electrostatic discharge

Vesd	Electrostatic discharge	On all pins.
	voltage.
	voltage.	Human body model.		[7]	−2000	+2000	V

		Machine model.		[8]	−200	+200	V

		Charged device model.			−500	+500	V

		On corner pins.

		Charged device model.			-750	+750	V

[1]Based on package heat transfer, not device power consumption.

[2]Peak current must be limited at 25 times average current.

[3]For I/O Port 0, the maximum input voltage is defined by VI(ADC).

[4]Only when VDD(IO) is present.

[5]Note that pull-up should be off. With pull-up do not exceed 3.6 V.

[6]In accordance with IEC 60747-1. An alternative definition of the virtual junction temperature is: Tvj = Tamb + Ptot ⋅ R a fixed value; see Section 10. The rating for Tvj limits the allowable combinations of power dissipation and ambient

[7]Human-body model: discharging a 100 pF capacitor via a 10 kΩ series resistor.

[8]Machine model: discharging a 200 pF capacitor via a 0.75 μH series inductance and 10 Ω resistor.

[9]112 mA per VDD(IO) or VSS(IO) should not be exceeded.

th(j-a) where Rth(j-a) is

temperature.

10. Thermal characteristics

Table 29.	Thermal characteristics
Symbol	Parameter	Conditions	Value	Unit
Rth(j-a)	thermal resistance from	in free air
	junction to ambient
	junction to ambient	package;
		package;

		LQFP144	62	K/W

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

52 of 68

Image 52

NXP Semiconductors LPC2919, LPC2917 user manual Thermal characteristics

Contents

Introduction General descriptionAbout this document Intended audience ARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Ordering information Ordering optionsOrdering information Part options Block diagram LPC2917/19 block diagram Pinning information PinningPin description General description Symbol Pin Description Function 0 default LQFP144 pin assignment … TIMER2 MAT2 PWM TRAP1 TIMER2 MAT3 PWM TRAP0TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1 Pin Description SymbolLQFP144 pin Reset, debug, test and power description Reset and power-up behaviorReset strategy Reset pin Ieee 1149.1 interface pins Jtag boundary-scan test Power supply pins descriptionClocking strategy Clock architecture LPC2917/19 block diagram, overview of clock areas LPC2917/19 Base clock and branch clock relationship Base clock and branch clock overviewBase clock Branch clock name Parts of the device clocked by This branch clock Block description Flash memory controllerOverview Base clock DRA Description Flash memory controller clock description Flash memory controller pin descriptionFlash layout Flash bridge wait-states Flash sector overview … External static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External memory timing diagrams External memory controller pinsExternal static-memory controller pin description External static-memory controller clock description Reading from external memory Writing to external memory Reading/writing external memory Chip and feature identification General subsystemGeneral subsystem clock description System Control Unit SCU Symbol Direction Bit position Description Default Polarity Peripheral subsystemPeripheral subsystem clock description Event-router pin connections Watchdog timer clock description TimerPin description 3.2 Description 3.3 Pin description Timer clock description Timer pinsUart pins UARTs Uart clock description Serial peripheral interfaceFunctional description SPI pins Modes of operationSPI pin description SPI clock description Gpio pins General-purpose I/O6.1 Overview Gpio pin description Can pins Can gatewayLIN Global acceptance filter LIN controller pins Modulation and sampling control subsystemLIN pin description LIN0/1 Txdl Synchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagram Start ADC conditions is valid Mscss pin description Mscss clock description Draft Analog-to-digital converter Analog to digital converter pins ADC block diagramADC pin description 6 PWM ADC clock description PWM block diagram Synchronizing the PWM counters Timers in the Mscss Master and slave modePWM pins PWM pin description Power, clock and reset control subsystem Mscss timer-clock descriptionMscss timer 1 pin Pause pin for Mscss timer PCR subsystem clock description Pcrss block diagramClock Generation Unit CGU CGU base clocks Number Name Frequency Description MHz Block diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset Generation Unit RGU Reset output configuration RGU pins Power Management Unit PMURGU pin description DRA Vectored interrupt controller PMU pin description VIC pin description Limiting valuesVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as input Analog-to-digital converter supply VDDA5V FSRINL LSB Dynamic characteristics Power-up resetDynamic characteristics Symbol Parameter Conditions Min Typ Max Unit UnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Package outline Package outline SOT486-1 LQFP144 Soldering IntroductionThrough-hole mount packages Surface mount packages Volume mm3 350 235 220 Lead-free process from J-STD-020C Temperature profiles for large and small componentsWave soldering SnPb eutectic process from J-STD-020C Package thickness mm Package related soldering information Mounting Package1 Soldering method Wave Reflow2 DippingCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SIL Mounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact information Contents Soldering Contact information ContentsPackage outline