PCR subsystem clock description | NXP Semiconductors LPC2917

NXP Semiconductors

AHB2DTL

Bridge

Fig 11. PCRSS block diagram

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

					DRA	DRAFT	DRA		DR
					F			F
					T			T
		t			DRAFT DRAFT DRAF
		t	Power, Clock & Reset			DRAFT DRAFT
	xo5 0m in	xo 50 m ou	Power, Clock & Reset

								DRAFT	D
									D
			CGU
		Xtal Oscillator		PMU				DRA
		Xtal Oscillator
			PLL	base
				base
			out0	clocks	Ga te s
			out1	C lo ck		branch
		Low Power	…			clocks
		Ring Oscillator	…			clocks
			out9

		(Ringo)
		(Ringo)
			FDIV[6:0]			AHB Master
			FDIV[6:0]	ble		Disable Grant
						Disable Grant
		CGU
		CGU		na
		registers		na
		registers		lock E	on trol
						AHB Master
						Disable Req
				C C		Disable Req
				C C
				reg		wakeup_a
				PM U _
			RGU

RGU	AHB_RST
registers	...
	...
	SCU_RST

Reset Output

Delay Logic

WARM_RST

COLD_RST

PCR_RST

RGU_RST

POR_RST

Input Deglitch/

POR

Sync

RSTN (device pin)

Reset from Watchdog counter

8.8.3PCR subsystem clock description

The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and PMU internal logic, see Section 7.2.2. CLK_SYS_PCRSS is derived from BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is derived from BASE_PCR_CLK and is always on in order to be able to wake up from low-power modes.

8.8.4Clock Generation Unit (CGU)

8.8.4.1Overview

The key features are:

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

41 of 68

Image 41

NXP Semiconductors LPC2917, LPC2919 PCR subsystem clock description, Clock Generation Unit CGU, Pcrss block diagram

Contents

General description IntroductionAbout this document Intended audience On-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Ordering options Ordering informationOrdering information Part options LPC2917/19 block diagram Block diagram Pinning Pinning informationPin description General description LQFP144 pin assignment … Symbol Pin Description Function 0 default TIMER2 MAT3 PWM TRAP0 TIMER2 MAT2 PWM TRAP1TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1 LQFP144 pin SymbolPin Description Reset and power-up behavior Reset, debug, test and power descriptionReset strategy Reset pin Power supply pins description Ieee 1149.1 interface pins Jtag boundary-scan testClocking strategy Clock architecture LPC2917/19 LPC2917/19 block diagram, overview of clock areas Base clock and branch clock overview Base clock and branch clock relationshipBase clock Branch clock name Parts of the device clocked by This branch clock Flash memory controller Block descriptionOverview Base clock Description DRA Flash layout Flash memory controller pin descriptionFlash memory controller clock description Flash sector overview … Flash bridge wait-states External memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External memory controller pins External memory timing diagramsExternal static-memory controller pin description External static-memory controller clock description Writing to external memory Reading from external memory Reading/writing external memory General subsystem Chip and feature identificationGeneral subsystem clock description System Control Unit SCU Peripheral subsystem Symbol Direction Bit position Description Default PolarityPeripheral subsystem clock description Event-router pin connections Pin description TimerWatchdog timer clock description 3.3 Pin description 3.2 Description Timer pins Timer clock descriptionUart pins UARTs Functional description Serial peripheral interfaceUart clock description Modes of operation SPI pinsSPI pin description SPI clock description General-purpose I/O Gpio pins6.1 Overview Gpio pin description Can gateway Can pinsLIN Global acceptance filter Modulation and sampling control subsystem LIN controller pinsLIN pin description LIN0/1 Txdl Modulation and sampling control subsystem block diagram Synchronization and trigger features of the Mscss Start ADC conditions is valid Mscss clock description Mscss pin description Analog-to-digital converter Draft ADC pin description ADC block diagramAnalog to digital converter pins ADC clock description 6 PWM Synchronizing the PWM counters PWM block diagram Master and slave mode Timers in the MscssPWM pins PWM pin description Mscss timer-clock description Power, clock and reset control subsystemMscss timer 1 pin Pause pin for Mscss timer Clock Generation Unit CGU Pcrss block diagramPCR subsystem clock description Number Name Frequency Description MHz CGU base clocks Block diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset output configuration Reset Generation Unit RGU RGU pin description Power Management Unit PMURGU pins DRA PMU pin description Vectored interrupt controller VIC clock description Limiting valuesVIC pin description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as input VDDA5V FSR Analog-to-digital converter supplyINL LSB Power-up reset Dynamic characteristicsDynamic characteristics Symbol Parameter Conditions Min Typ Max Unit UnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter Specification Package outline SOT486-1 LQFP144 Package outline Introduction SolderingThrough-hole mount packages Surface mount packages Temperature profiles for large and small components Volume mm3 350 235 220 Lead-free process from J-STD-020CWave soldering SnPb eutectic process from J-STD-020C Package thickness mm Mounting Package1 Soldering method Wave Reflow2 Dipping Package related soldering informationCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SIL Mounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal information Contents Package outline Contact information ContentsSoldering