Base clock and branch clock overview | NXP Semiconductors LPC2917

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

				DRA		DRA				DR
				F			F
	7.2.2 Base clock and branch clock relationship			T DRAFT				T
	7.2.2 Base clock and branch clock relationship			DRAFT DRAFT DRAF
				DRAFT DRAFT DRAF
		The next table contains an overview of all the base blocks in the LPC2917/19 and their
		derived branch clocks. A short description is given of the hardware parts that are clocked
					DRAFT		DRAFT
		with the individual branch clocks. In relevant cases more detailed information can be								D
		found in the specific subsystem description. Some branch clocks have special protection								D

						DRAFT
		since they clock vital system parts of the device and should (for example) not be switched							DRA
		off. See Section 8.8.6 for more details of how to control the individual branch clocks.							DRA
		Table 7. Base clock and branch clock overview

		Base clock	Branch clock name	Parts of the device clocked by	Remark
				this branch clock
		BASE_SAFE_CLK	CLK_SAFE	Watchdog Timer	[1]

		BASE_SYS_CLK	CLK_SYS_CPU	ARM968E-S and TCMs

			CLK_SYS_SYS	AHB Bus infrastructure

			CLK_SYS_PCRSS	AHB side of bridge in PCRSS

			CLK_SYS_FMC	Flash-Memory Controller

			CLK_SYS_RAM0	Embedded SRAM Controller 0
				(32 KByte)

			CLK_SYS_RAM1	Embedded SRAM Controller 1
				(16 KByte)
			CLK_SYS_SMC	External Static-Memory
				Controller

			CLK_SYS_GESS	General Subsystem

			CLK_SYS_VIC	Vectored Interrupt Controller

			CLK_SYS_PESS	Peripheral Subsystem	[2] [4]

			CLK_SYS_GPIO0	GPIO bank 0

			CLK_SYS_GPIO1	GPIO bank 1

			CLK_SYS_GPIO2	GPIO bank 2

			CLK_SYS_GPIO3	GPIO bank 3

			CLK_SYS_IVNSS_A	AHB side of bridge of IVNSS

		BASE_PCR_CLK	CLK_PCR_SLOW	PCRSS, CGU, RGU and PMU	[1], [3]
				logic clock

		BASE_IVNSS_CLK	CLK_IVNSS_VPB	VPB side of the IVNSS

			CLK_IVNSS_CANCA	CAN controller Acceptance Filter

			CLK_IVNSS_CANC0	CAN channel 0

			CLK_IVNSS_CANC1	CAN channel 1

			CLK_IVNSS_LIN0	LIN channel 0

			CLK_IVNSS_LIN1	LIN channel 1

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

13 of 68

Image 13

NXP Semiconductors LPC2917, LPC2919 Base clock and branch clock relationship, Base clock and branch clock overview

Contents

General description IntroductionAbout this document Intended audience ARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Ordering options Ordering informationOrdering information Part options LPC2917/19 block diagram Block diagram Pinning Pinning informationPin description General description LQFP144 pin assignment … Symbol Pin Description Function 0 default TIMER2 MAT3 PWM TRAP0 TIMER2 MAT2 PWM TRAP1TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1 Pin Description SymbolLQFP144 pin Reset and power-up behavior Reset, debug, test and power descriptionReset strategy Reset pin Power supply pins description Ieee 1149.1 interface pins Jtag boundary-scan testClocking strategy Clock architecture LPC2917/19 LPC2917/19 block diagram, overview of clock areas Base clock and branch clock overview Base clock and branch clock relationshipBase clock Branch clock name Parts of the device clocked by This branch clock Flash memory controller Block descriptionOverview Base clock Description DRA Flash memory controller clock description Flash memory controller pin descriptionFlash layout Flash sector overview … Flash bridge wait-states External static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External memory controller pins External memory timing diagramsExternal static-memory controller pin description External static-memory controller clock description Writing to external memory Reading from external memory Reading/writing external memory General subsystem Chip and feature identificationGeneral subsystem clock description System Control Unit SCU Peripheral subsystem Symbol Direction Bit position Description Default PolarityPeripheral subsystem clock description Event-router pin connections Watchdog timer clock description TimerPin description 3.3 Pin description 3.2 Description Timer pins Timer clock descriptionUart pins UARTs Uart clock description Serial peripheral interfaceFunctional description Modes of operation SPI pinsSPI pin description SPI clock description General-purpose I/O Gpio pins6.1 Overview Gpio pin description Can gateway Can pinsLIN Global acceptance filter Modulation and sampling control subsystem LIN controller pinsLIN pin description LIN0/1 Txdl Modulation and sampling control subsystem block diagram Synchronization and trigger features of the Mscss Start ADC conditions is valid Mscss clock description Mscss pin description Analog-to-digital converter Draft Analog to digital converter pins ADC block diagramADC pin description ADC clock description 6 PWM Synchronizing the PWM counters PWM block diagram Master and slave mode Timers in the MscssPWM pins PWM pin description Mscss timer-clock description Power, clock and reset control subsystemMscss timer 1 pin Pause pin for Mscss timer PCR subsystem clock description Pcrss block diagramClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocks Block diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset output configuration Reset Generation Unit RGU RGU pins Power Management Unit PMURGU pin description DRA PMU pin description Vectored interrupt controller VIC pin description Limiting valuesVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as input VDDA5V FSR Analog-to-digital converter supplyINL LSB Power-up reset Dynamic characteristicsDynamic characteristics Symbol Parameter Conditions Min Typ Max Unit UnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter Specification Package outline SOT486-1 LQFP144 Package outline Introduction SolderingThrough-hole mount packages Surface mount packages Temperature profiles for large and small components Volume mm3 350 235 220 Lead-free process from J-STD-020CWave soldering SnPb eutectic process from J-STD-020C Package thickness mm Mounting Package1 Soldering method Wave Reflow2 Dipping Package related soldering informationCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SIL Mounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal information Contents Soldering Contact information ContentsPackage outline