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NXP Semiconductors LPC2919 user manual Peripheral subsystem clock description, DLPC2917/19

Models: LPC2917 LPC2919

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8.3.4.2 Description

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

•Event detection is fully asynchronous, so no clock is required

T DRAFT	T
DRA	DRA DR
F	F
DRAFT DRAFT DRAF

The event router allows the event source to be defined, its polarity and activationDRAFTtype to DRAFT

be selected and the interrupt to be masked or enabled. The event router can be used to		D
start a clock on an external event.	DRAFT

The vectored interrupt-controller inputs are active HIGH.

8.3.4.3Event-router pin description and mapping to register bit positions

DRA

The event router module in the LPC2917/19 is connected to the pins listed below. The pins are combined with other functions on the port pins of the LPC2917/19. Table 13 shows the pins connected to the event router, and also the corresponding bit position in the event-router registers and the default polarity.

Table 13. Event-router pin connections

Symbol	Direction	Bit position	Description	Default
				polarity
EXTINT0	in	0	external interrupt input 0	1

EXTINT1	in	1	external interrupt input 1	1

EXTINT2	in	2	external interrupt input 2	1

EXTINT3	in	3	external interrupt input 3	1

EXTINT4	in	4	external interrupt input 4	1

EXTINT5	in	5	external interrupt input 5	1

EXTINT6	in	6	external interrupt input 6	1

EXTINT7	in	7	external interrupt input 7	1

CAN0 RXD	in	8	CAN0 receive data input wake-up	0

CAN1 RXD	in	9	CAN1 receive data input wake-up	0

-	-	13 - 10	reserved	-

LIN0 RXD	in	14	LIN0 receive data input wake-up	0

LIN1 RXD	in	15	LIN1 receive data input wake-up	0

-	-	21 - 16	reserved	-

-	na	22	CAN interrupt (internal)	1

-	na	23	VIC FIQ (internal)	1

-	na	24	VIC IRQ (internal)	1

-	-	26 - 25	reserved	-

8.4Peripheral subsystem

8.4.1Peripheral subsystem clock description

The peripheral subsystem is clocked by a number of different clocks:

•CLK_SYS_PESS

•CLK_UART0/1

•CLK_SPI0/1/2

•CLK_TMR0/1/2/3

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

23 of 68

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NXP Semiconductors LPC2919 user manual Peripheral subsystem clock description, DLPC2917/19

Contents

LPC2917/19 1. Introduction2. General description T DRAFT DLPC2917/19DLPC2917/19 3. FeaturesDLPC2917/19 4. Ordering informationPreliminary data sheet 5. Block diagramDRA DR DRAFT DRAFTDLPC2917/19 6. Pinning information6.2.1 General description 6.2.2 LQFP144 pin assignmentRAFT AFT SymbolFunction 0 default DLPC2917/19RAFT AFT SymbolFunction 0 default DLPC2917/19DRAFT DLPC2917/19LQFP144 pin 7. Functional description 7.1 Reset, debug, test and power description7.1.1 Reset and power-up behavior 7.1.2 Reset strategyDLPC2917/19 7.1.3 IEEE 1149.1 interface pins JTAG boundary-scan test7.1.4 Power supply pins description 7.2.1 Clock architectureRAFT AFT DRAFPreliminary data sheet DLPC2917/19Table 7. Base clock and branch clock overview 7.2.2 Base clock and branch clock relationshipDLPC2917/19 DRAFT DRAFT DRAFDLPC2917/19 8. Block description8.1.1 Overview DLPC2917/19 8.1.2 DescriptionDLPC2917/19 8.1.3 Flash memory controller pin description8.1.4 Flash memory controller clock description 8.1.5 Flash layoutTable 9. Flash sector overview …continued 8.1.6 Flash bridge wait-statesDLPC2917/19 DRAFT DRAFTDLPC2917/19 8.2.1 Overview8.2.2 Description Table 12. External memory controller pins 8.2.5 External memory timing diagrams8.2.3 External static-memory controller pin description 8.2.4 External static-memory controller clock descriptionDLPC2917/19 DRAFT DRAFTDRAFT DRAFT DRAF Preliminary data sheetNXP Semiconductors DLPC2917/19RAFT AFT T DRAFT8.3.4 Event router 8.3.2 Chip and feature identification8.3.1 General subsystem clock description 8.3.3 System Control Unit SCUDLPC2917/19 8.4.1 Peripheral subsystem clock description8.4.2.2 Description 8.4.3 Timer8.4.2.4 Watchdog timer clock description 8.4.2.1 OverviewPin description 8.4.3.2Description 8.4.3.38.4.4.2 Description 8.4.3.4 Timer clock description8.4.4 UARTs 8.4.4.1 Overview8.4.5.2 Functional description 8.4.5 Serial peripheral interface8.4.4.4 UART clock description 8.4.5.1 OverviewDLPC2917/19 8.4.5.3 Modes of operation8.4.5.4 SPI pin description 8.4.5.5 SPI clock descriptionOverview 8.4.6General-purpose I/O 8.4.6.18.5.3 CAN pin description 8.5.1Overview 8.5.2 Global acceptance filterDLPC2917/19 8.6.2 LIN pin description8.7.1 Overview 8.7.2 DescriptionDLPC2917/19 8.7.2.1 Synchronization and trigger features of the MSCSST DRAFT start ADC conditions is validDLPC2917/19 RAFT AFTThe MSCSS is clocked from a number of different sources 8.7.3 MSCSS pin description8.7.4 MSCSS clock description DLPC2917/19DLPC2917/19 8.7.5 Analog-to-digital converter8.7.5.1 Overview 8.7.5.2 DescriptionT DRAFT 8.7.5.3 ADC pin descriptionDLPC2917/19 RAFT AFT8.7.6.2 Description 8.7.6 PWM8.7.5.4 ADC clock description 8.7.6.1 OverviewDLPC2917/19 8.7.6.3 Synchronizing the PWM countersFig 10. PWM block diagram 8.7.6.6 PWM clock description 8.7.7 Timers in the MSCSS8.7.6.4 Master and slave mode 8.7.6.5 PWM pin description8.7.7.2 Description 8.7.7.4 MSCSS timer-clock description8.8.1 Overview 8.8.2 DescriptionDLPC2917/19 8.8.3 PCR subsystem clock description8.8.4 Clock Generation Unit CGU Power, Clock & ResetT DRAFT 8.8.4.2 DescriptionDLPC2917/19 RAFT AFTT DRAFT DLPC2917/19RAFT AFT DRA DRLPOSC/crystal Oscillator DLPC2917/19DRAFT DRAFT DRAF T DRAFT 8.8.4.3 PLL functional descriptionDLPC2917/19 RAFT AFTDLPC2917/19 8.8.4.4 CGU pin descriptionTriple output phases Power-down controlDLPC2917/19 8.8.5 Reset Generation Unit RGU8.8.5.1 Overview 8.8.5.2 Description8.8.6.2 Description 8.8.6 Power Management Unit PMU8.8.5.3 RGU pin description 8.8.6.1 OverviewImplemented Switch On/Off DRAFT DRAFTDRAFT DRAFDRAFT DRAFT 8.9 Vectored interrupt controller8.9.1 Overview 8.9.2 DescriptionDLPC2917/19 9. Limiting values8.9.3 VIC pin description 8.9.4 VIC clock descriptionSymbol 10. Thermal characteristicsDRAFTmA DRAFTRAFT AFT 11. Static characteristicsSymbol DLPC2917/19Symbol DRAFTUnitDRAFT Table 30. Static characteristics …continuedSymbol 12. Dynamic characteristicsTable 30. Static characteristics …continued SymbolDRAFT UnitDRAFTDLPC2917/19 DRAFT DRAFTDLPC2917/19 Table 31. Dynamic characteristics …continuedSymbol Jitter SpecificationRAFT AFT 13. Package outlinePreliminary data sheet DLPC2917/1914.3 Surface mount packages 14. Soldering14.1 Introduction 14.2 Through-hole mount packagesMSL Moisture Sensitivity Level 14.3.2 Wave solderingDLPC2917/19 DRAFT DRAFTDLPC2917/19 14.3.3 Manual solderingDipping DLPC2917/19Package1 Soldering methodDRA DR 15. AbbreviationsDLPC2917/19 RAFT AFTDRA DR 16. ReferencesDLPC2917/19 RAFT AFTTable 36. Revision history 17. Revision historyDLPC2917/19 DRAFT DRAFT DRAFFor sales office addresses, send an email to salesaddresses@nxp.com 18. Legal information19. Contact information DLPC2917/19DLPC2917/19 20. Contentscontinued 19 Contact information 20 Contents T DRAFT9 Limiting values 10 Thermal characteristics 11 Static characteristics 12 Dynamic characteristics